| 1 | /* entry.s |
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| 2 | * |
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| 3 | * This file contains the entry point for the application. |
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| 4 | * The name of this entry point is compiler dependent. |
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| 5 | * It jumps to the BSP which is responsible for performing |
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| 6 | * all initialization. |
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| 7 | * |
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| 8 | * COPYRIGHT (c) 1989-1999. |
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| 9 | * On-Line Applications Research Corporation (OAR). |
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| 10 | * |
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| 11 | * The license and distribution terms for this file may be |
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| 12 | * found in the file LICENSE in this distribution or at |
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| 13 | * http://www.OARcorp.com/rtems/license.html. |
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| 14 | * |
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| 15 | * $Id$ |
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| 16 | */ |
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| 17 | |
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| 18 | #include "asm.h" |
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| 19 | |
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| 20 | .set BAR, 0xF2 | Base Address Register location |
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| 21 | .set SCR, 0xF4 | System Control Register location |
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| 22 | .set BAR_VAL, 0x0f7f | BAR value |
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| 23 | .set SCR_VAL, 0x00080f00 | SCR value |
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| 24 | .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). |
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| 25 | .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address |
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| 26 | |
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| 27 | .set oSYSRAM, 0x000 | 576 bytes of internal system RAM |
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| 28 | |
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| 29 | .set oGIMR, 0x812 |
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| 30 | |
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| 31 | .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg |
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| 32 | .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg |
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| 33 | .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg |
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| 34 | .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg |
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| 35 | .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg |
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| 36 | .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg |
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| 37 | .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg |
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| 38 | .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg |
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| 39 | |
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| 40 | .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM |
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| 41 | .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location |
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| 42 | |
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| 43 | |
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| 44 | BEGIN_CODE |
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| 45 | PUBLIC (M68Kvec) | Vector Table |
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| 46 | SYM (M68Kvec): | standard location for vectors |
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| 47 | V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP |
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| 48 | V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC |
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| 49 | V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error |
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| 50 | V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error |
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| 51 | .space 240 | reserve space for reset of vectors |
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| 52 | |
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| 53 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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| 54 | SYM (lowintstack): |
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| 55 | .space 4092 | reserve for interrupt stack |
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| 56 | SYM (hiintstack): |
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| 57 | .space 4 | end of interrupt stack |
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| 58 | #endif |
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| 59 | |
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| 60 | PUBLIC (start) | Default entry point for GNU |
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| 61 | SYM (start): |
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| 62 | move.w #0x2700,sr | Disable all interrupts |
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| 63 | move.w #BAR_VAL,BAR | Set Base Address Register |
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| 64 | move.l #SCR_VAL,SCR | Set System Control Register |
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| 65 | lea BaseAddr,a5 |
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| 66 | move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register |
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| 67 | |
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| 68 | | |
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| 69 | | Set up chip select registers for the remapping process. |
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| 70 | | |
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| 71 | |
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| 72 | | |
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| 73 | | 0 X x x x x |
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| 74 | | 0 000 0 0-- - --- ---- ---- ---- |
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| 75 | | x xxx x xxx x xx |
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| 76 | | |
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| 77 | move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) |
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| 78 | move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS |
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| 79 | |
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| 80 | | |
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| 81 | | X x x x x x |
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| 82 | | 0 100 0 0-- - --- ---- ---- ---- |
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| 83 | | x xxx x xxx x xx |
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| 84 | | |
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| 85 | move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) |
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| 86 | move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS |
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| 87 | |
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| 88 | | |
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| 89 | | Copy the initial boot FLASH area to the temporary SRAM location. |
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| 90 | | |
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| 91 | moveq #0,d0 |
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| 92 | movea.l d0,a0 | a0 -> start of FLASH |
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| 93 | lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM |
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| 94 | | moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy |
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| 95 | moveq #127,d0 |
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| 96 | cpy_flash: move.l (a0)+,(a1)+ | copy |
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| 97 | subq.l #1,d0 |
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| 98 | bne cpy_flash |
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| 99 | |
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| 100 | | |
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| 101 | | Copy remap code to 68302''s internal system RAM. |
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| 102 | | |
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| 103 | movea.w #begRemap-V___ISSP,a0 | a0 -> remap code |
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| 104 | lea a5@(oSYSRAM),a1 | a1 -> internal system RAM |
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| 105 | | moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy |
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| 106 | moveq #11,d0 |
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| 107 | cpy_remap: move.w (a0)+,(a1)+ | copy |
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| 108 | dbra d0,cpy_remap |
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| 109 | |
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| 110 | | |
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| 111 | | Jump to the remap code in the 68302''s internal system RAM. |
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| 112 | | |
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| 113 | jmp a5@(oSYSRAM) | (effectively a jmp begRemap) |
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| 114 | |
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| 115 | | |
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| 116 | | This remap code, when executed from the 68302''s internal system RAM |
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| 117 | | will 1) remap CS1 so that SRAM is at 0 |
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| 118 | | 2) remap CS0 so that FLASH is at FLASH_BASE |
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| 119 | | and 3) jump to executable code in the remapped FLASH. |
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| 120 | | |
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| 121 | begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) |
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| 122 | move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) |
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| 123 | lea FLASH_BASE,a0 |
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| 124 | jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH |
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| 125 | endRemap: |
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| 126 | | |
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| 127 | | Now set up the remaining chip select registers. |
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| 128 | | |
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| 129 | |
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| 130 | | |
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| 131 | | 4 0 x x x x |
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| 132 | | 1 000 1 111 0 000 0--- ---- ---- |
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| 133 | | x xxx x xxx x xx |
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| 134 | | |
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| 135 | move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) |
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| 136 | move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS |
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| 137 | |
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| 138 | | |
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| 139 | | 8 X x x x x |
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| 140 | | 1 000 0 0-- - --- ---- ---- ---- |
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| 141 | | x xxx x xxx x xx |
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| 142 | | |
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| 143 | move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) |
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| 144 | move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS |
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| 145 | |
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| 146 | endPreBoot: |
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| 147 | |
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| 148 | move.b #0x30,0x800001 | set status LED amber |
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| 149 | |
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| 150 | .set oPIOB_Ctrl, 0x824 |
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| 151 | .set oPIOB_DDR, 0x826 |
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| 152 | .set oPIOB_Data, 0x828 |
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| 153 | |
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| 154 | .set oPIOA_Ctrl, 0x81e |
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| 155 | .set oPIOA_DDR, 0x820 |
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| 156 | .set oPIOA_Data, 0x822 |
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| 157 | |
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| 158 | move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. |
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| 159 | move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. |
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| 160 | move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated |
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| 161 | | peripheral pins. |
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| 162 | |
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| 163 | move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. |
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| 164 | move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. |
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| 165 | move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated |
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| 166 | | peripheral pins. |
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| 167 | |
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| 168 | | |
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| 169 | | Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 |
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| 170 | | are not set because they are the 68302''s BAR and SCR. |
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| 171 | | |
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| 172 | movea.w #0x010,a0 |
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| 173 | moveq #(0x0f0-0x010)/4-1,d0 |
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| 174 | move.l #Bad,d1 |
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| 175 | cpy_Bad: move.l d1,(a0)+ |
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| 176 | dbra d0,cpy_Bad |
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| 177 | |
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| 178 | .set vbase, 0x0200 |
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| 179 | |
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| 180 | lea vbase,a0 |
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| 181 | moveq #31,d0 |
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| 182 | cpy_Bad1: move.l d1,(a0)+ |
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| 183 | dbra d0,cpy_Bad1 |
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| 184 | |
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| 185 | | |
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| 186 | | Fill in special locations to configure OS |
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| 187 | | |
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| 188 | move.l #Bad,0x008 | Bus Error |
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| 189 | move.l #Bad,0x00c | Address Error |
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| 190 | move.l #Bad,0x024 | Trace |
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| 191 | | move.l #KE_IRET,$0b4 | pSOS+ RET_I Call |
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| 192 | |
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| 193 | | move.l #_cnsl_isr,vbase+0x028 | SCC2 |
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| 194 | move.l #timerisr,vbase+0x018 | Timer ISR |
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| 195 | |
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| 196 | | |
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| 197 | | zero out uninitialized data area |
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| 198 | | |
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| 199 | zerobss: |
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| 200 | moveal # SYM (_clear_end),a0 | find end of .bss |
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| 201 | moveal # SYM (_clear_start),a1 | find beginning of .bss |
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| 202 | moveq #0,d0 |
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| 203 | |
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| 204 | loop: movel d0,a1@+ | to zero out uninitialized |
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| 205 | cmpal a0,a1 |
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| 206 | jlt loop | loop until _clear_end reached |
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| 207 | |
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| 208 | movel d0, SYM (_stack_init) | Set Stack pointer |
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| 209 | movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! |
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| 210 | movel d0,a7 | set master stack pointer |
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| 211 | movel d0,a6 | set base pointer |
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| 212 | |
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| 213 | /* |
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| 214 | * RTEMS should maintain a separate interrupt stack on CPUs |
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| 215 | * without one in hardware. This is currently not supported |
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| 216 | * on versions of the m68k without a HW intr stack. |
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| 217 | */ |
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| 218 | |
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| 219 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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| 220 | lea SYM (hiintstack),a0 | a0 = high end of intr stack |
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| 221 | movec a0,isp | set interrupt stack |
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| 222 | #endif |
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| 223 | |
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| 224 | move.l #0,a7@- | environp |
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| 225 | move.l #0,a7@- | argv |
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| 226 | move.l #0,a7@- | argc |
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| 227 | jsr SYM (boot_card) |
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| 228 | |
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| 229 | nop |
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| 230 | Bad: bra Bad |
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| 231 | |
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| 232 | nop |
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| 233 | END_CODE |
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| 234 | |
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| 235 | |
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| 236 | BEGIN_DATA |
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| 237 | |
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| 238 | PUBLIC (start_frame) |
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| 239 | SYM (start_frame): |
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| 240 | .space 4,0 |
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| 241 | |
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| 242 | PUBLIC (stack_start) |
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| 243 | SYM (stack_start): |
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| 244 | .space 4,0 |
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| 245 | END_DATA |
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| 246 | |
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| 247 | BEGIN_BSS |
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| 248 | |
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| 249 | PUBLIC (environ) |
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| 250 | .align 2 |
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| 251 | SYM (environ): |
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| 252 | .long 0 |
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| 253 | |
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| 254 | PUBLIC (heap_size) |
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| 255 | .set SYM (heap_size),0x2000 |
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| 256 | |
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| 257 | PUBLIC (stack_size) |
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| 258 | .set SYM (stack_size),0x1000 |
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| 259 | |
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| 260 | |
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| 261 | END_DATA |
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| 262 | END |
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