1 | /* |
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2 | * Implements the Motorola 68302 multi-protocol chip parameter |
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3 | * definition header. |
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4 | * |
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5 | * $Id$ |
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6 | */ |
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7 | |
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8 | #ifndef __M302_INT_h |
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9 | #define __M302_INT_h |
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10 | |
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11 | #ifndef uchar |
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12 | #define uchar unsigned char |
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13 | #endif |
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14 | #ifndef ushort |
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15 | #define ushort unsigned short |
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16 | #endif |
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17 | #ifndef ulong |
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18 | #define ulong unsigned long |
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19 | #endif |
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20 | |
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21 | /* Ethernet Control Register ECNTRL */ |
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22 | #define ECNTRL_BIT_RESET 0x0001 |
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23 | #define ECNTRL_BIT_ETHER_EN 0x0002 |
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24 | #define ECNTRL_BIT_GTS 0x0004 |
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25 | |
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26 | /* Ethernet DMA Configuration Status Register EDMA */ |
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27 | #define EDMA_BDERR_MASK 0xFE00 |
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28 | |
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29 | #define EDMA_BDSIZE_MASK 0x00C0 |
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30 | #define EDMA_BDSIZE_8T_120R 0x0000 |
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31 | #define EDMA_BDSIZE_16T_112R 0x0040 |
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32 | #define EDMA_BDSIZE_32T_96R 0x0080 |
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33 | #define EDMA_BDSIZE_64T_64R 0x00C0 |
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34 | |
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35 | #define EDMA_BIT_TSRLY 0x0020 |
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36 | |
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37 | #define EDMA_WMRK_MASK 0x0018 |
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38 | #define EDMA_WMRK_8FIFO 0x0000 |
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39 | #define EDMA_WMRK_16FIFO 0x0008 |
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40 | #define EDMA_WMRK_24FIFO 0x0010 |
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41 | #define EDMA_WMRK_32FIFO 0x0018 |
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42 | |
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43 | #define EDMA_BLIM_MASK 0x0007 |
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44 | #define EDMA_BLIM_8ACCESS 0x0003 |
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45 | |
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46 | |
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47 | /* Ethernet Maximum Receive Buffer Length EMRBLR */ |
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48 | #define EMRBLR_MASK 0x07FFE |
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49 | |
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50 | /* Interrupt Vector Register IVEC */ |
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51 | #define IVEC_BIT_VG 0x0100 |
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52 | #define IVEC_INV_MASK 0x00FF |
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53 | |
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54 | /* Interrupt Event Register INTR_EVENT */ |
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55 | #define INTR_EVENT_BIT_RXB 0x0001 |
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56 | #define INTR_EVENT_BIT_TXB 0x0002 |
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57 | #define INTR_EVENT_BIT_BSY 0x0004 |
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58 | #define INTR_EVENT_BIT_RFINT 0x0008 |
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59 | #define INTR_EVENT_BIT_TFINT 0x0010 |
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60 | #define INTR_EVENT_BIT_EBERR 0x0020 |
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61 | #define INTR_EVENT_BIT_BOD 0x0040 |
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62 | #define INTR_EVENT_BIT_GRA 0x0080 |
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63 | #define INTR_EVENT_BIT_BABT 0x0100 |
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64 | #define INTR_EVENT_BIT_BABR 0x0200 |
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65 | #define INTR_EVENT_BIT_HBERR 0x0400 |
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66 | |
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67 | /* Interrupt Mask Register INTR_MASK */ |
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68 | #define INTR_MASK_BIT_RXIEN 0x0001 |
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69 | #define INTR_MASK_BIT_TXIEN 0x0002 |
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70 | #define INTR_MASK_BIT_BSYEN 0x0004 |
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71 | #define INTR_MASK_BIT_RFIEN 0x0008 |
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72 | #define INTR_MASK_BIT_TFIEN 0x0010 |
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73 | #define INTR_MASK_BIT_EBERREN 0x0020 |
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74 | #define INTR_MASK_BIT_BODEN 0x0040 |
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75 | #define INTR_MASK_BIT_GRAEN 0x0080 |
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76 | #define INTR_MASK_BIT_BTEN 0x0100 |
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77 | #define INTR_MASK_BIT_BREN 0x0200 |
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78 | #define INTR_MASK_BIT_HBEEN 0x0400 |
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79 | |
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80 | /* Ethernet Configuration ECNFIG */ |
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81 | #define ECNFIG_BIT_LOOP 0x0001 |
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82 | #define ECNFIG_BIT_FDEN 0x0002 |
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83 | #define ECNFIG_BIT_HBC 0x0004 |
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84 | #define ECNFIG_BIT_RDT 0x0008 |
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85 | |
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86 | /* Ethernet Test ETHER_TEST */ |
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87 | #define ETHER_TEST_BIT_TWS 0x0001 |
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88 | #define ETHER_TEST_BIT_RWS 0x0002 |
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89 | #define ETHER_TEST_BIT_DRTY 0x0004 |
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90 | #define ETHER_TEST_BIT_COLL 0x0008 |
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91 | #define ETHER_TEST_BIT_SLOT 0x0010 |
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92 | #define ETHER_TEST_BIT_TRND 0x0020 |
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93 | #define ETHER_TEST_BIT_TBO 0x0040 |
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94 | #define ETHER_TEST_BIT_RNGT 0x0080 |
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95 | #define ETHER_TEST_REV_MASK 0xF000 |
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96 | |
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97 | /* Ethernet AR Control Registere AR_CNTRL */ |
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98 | #define AR_CNTRL_BIT_PROM 0x0400 |
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99 | #define AR_CNTRL_BIT_PA_REJ 0x0800 |
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100 | #define AR_CNTRL_BIT_NO_BROADCAST 0x1000 |
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101 | #define AR_CNTRL_BIT_MULTI1 0x2000 |
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102 | #define AR_CNTRL_BIT_INDEX_EN 0x4000 |
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103 | #define AR_CNTRL_BIT_HASH_EN 0x8000 |
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104 | |
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105 | #define AR_CNTRL_MULTI_MASK (AR_CNTRL_BIT_MULTI0 | AR_CNTRL_BIT_MULTI1) |
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106 | |
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107 | |
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108 | /* Ethernet buffer Status TX */ |
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109 | #define BUF_STAT_CARRIER_LOST 0x0001 |
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110 | #define BUF_STAT_UNDERRUN 0x0002 |
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111 | #define BUF_STAT_RETRANS_COUNT 0x003C |
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112 | #define BUF_STAT_RETRY_LIMIT 0x0040 |
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113 | #define BUF_STAT_LATE_COLLISION 0x0080 |
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114 | #define BUF_STAT_HEARTBIT 0x0100 |
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115 | #define BUF_STAT_DEFER 0x0200 |
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116 | #define BUF_STAT_TX_CRC 0x0400 |
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117 | #define BUF_STAT_LAST 0x0800 |
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118 | #define BUF_STAT_INTERRUPT 0x1000 |
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119 | #define BUF_STAT_WRAP 0x2000 |
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120 | #define BUF_STAT_TO 0x4000 |
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121 | #define BUF_STAT_READY 0x8000 |
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122 | |
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123 | |
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124 | /* Ethernet buffer Status RX */ |
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125 | #define BUF_STAT_COLLISION 0x0001 |
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126 | #define BUF_STAT_OVERRUN 0x0002 |
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127 | #define BUF_STAT_CRC_ERROR 0x0004 |
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128 | #define BUF_STAT_SHORT 0x0008 |
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129 | #define BUF_STAT_NONALIGNED 0x0010 |
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130 | #define BUF_STAT_LONG 0x0020 |
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131 | #define BUF_STAT_FIRST_IN_FRAME 0x0400 |
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132 | #define BUF_STAT_EMPTY 0x8000 |
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133 | |
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134 | /* SCC Buffer Descriptor structure |
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135 | ----------------------------------*/ |
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136 | |
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137 | struct m68302_scc_bd { |
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138 | ushort stat_ctrl; |
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139 | ushort data_lgth; |
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140 | uchar *p_buffer; |
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141 | }; |
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142 | |
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143 | #define M68302_scc_bd_stat_ctrl(p) \ |
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144 | (((struct m68302_scc_bd *)(p)) -> stat_ctrl) |
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145 | #define M68302_scc_bd_data_lgth(p) \ |
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146 | (((struct m68302_scc_bd *)(p)) -> data_lgth) |
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147 | #define M68302_scc_bd_p_buffer(p) \ |
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148 | (((struct m68302_scc_bd *)(p)) -> p_buffer) |
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149 | |
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150 | struct m68302_imp { |
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151 | |
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152 | /* BASE : user data memory */ |
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153 | |
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154 | uchar user_data[0x240]; /* 0x240 bytes user data */ |
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155 | uchar user_reserved[0x1c0]; /* empty till 0x400 */ |
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156 | |
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157 | /* BASE + 400H: PARAMETER RAM */ |
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158 | struct { |
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159 | struct m68302_scc_bd scc_bd_rx[8]; /* Rx buffer descriptors */ |
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160 | struct m68302_scc_bd scc_bd_tx[8]; /* Tx buffer descriptors */ |
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161 | |
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162 | uchar rfcr; /* Rx function code */ |
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163 | uchar tfcr; /* Tx function code */ |
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164 | ushort mrblr; /* maximum Rx buffer length */ |
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165 | ushort rist; /* internal state */ |
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166 | uchar res1; |
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167 | uchar rbdn; /* Rx internal buffer number */ |
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168 | ulong ridp; |
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169 | ushort ribc; |
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170 | ushort rtmp; |
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171 | ushort tist; |
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172 | uchar res2; |
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173 | uchar tbdn; /* Tx internal buffer number */ |
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174 | ulong tidp; |
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175 | ushort tibc; |
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176 | ushort ttmp; |
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177 | |
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178 | unsigned char scc_spp [0x64]; /* SCC specific parameters */ |
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179 | } parm_ram [3]; |
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180 | |
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181 | uchar reserved_1 [0x100]; |
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182 | |
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183 | /* BASE + 800H: INTERNAL REGISTERS */ |
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184 | |
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185 | /* DMA */ |
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186 | |
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187 | ushort dma_res1; /* reserved */ |
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188 | ushort dma_mode; /* dma mode reg */ |
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189 | ulong dma_src; /* dma source */ |
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190 | ulong dma_dest; /* dma destination */ |
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191 | ushort dma_count; /* dma byte count */ |
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192 | uchar dma_status; /* dma status */ |
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193 | uchar dma_res2; /* reserved */ |
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194 | uchar dma_fct_code; /* dma function code */ |
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195 | uchar dma_res3; /* reserved */ |
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196 | |
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197 | /* Interrupt Controller */ |
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198 | |
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199 | ushort it_mode; /* interrupt mode register */ |
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200 | ushort it_pending; /* interrupt pending register */ |
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201 | ushort it_mask; /* interrupt mask register */ |
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202 | ushort it_inservice; /* interrupt in service register */ |
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203 | ulong it_reserved; /* reserved */ |
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204 | |
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205 | /* Parallel I/O */ |
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206 | |
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207 | struct { |
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208 | ushort control; /* port control register */ |
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209 | ushort direction; /* port data direction register */ |
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210 | ushort data; /* port data value register */ |
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211 | } port[2]; |
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212 | |
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213 | ushort p_reserved; /* reserved */ |
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214 | |
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215 | /* Chip Select */ |
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216 | |
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217 | ulong cs_reserved; |
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218 | |
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219 | struct { |
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220 | ushort base; /* chip select base register */ |
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221 | ushort option; /* chip select option register */ |
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222 | } cs[4]; |
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223 | |
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224 | /* Timer */ |
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225 | |
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226 | ushort t1_mode; /* timer 1 mode register */ |
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227 | ushort t1_reference; /* timer 1 reference register */ |
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228 | ushort t1_capture; /* timer 1 capture register */ |
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229 | ushort t1_counter; /* timer 1 counter */ |
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230 | uchar tim_res1; /* reserved */ |
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231 | uchar t1_event; /* timer 1 event */ |
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232 | |
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233 | ushort t3_reference; /* timer 3 reference register */ |
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234 | ushort t3_counter; /* timer 3 counter */ |
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235 | ushort tim_res2; /* reserved */ |
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236 | |
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237 | ushort t2_mode; /* timer 2 mode register */ |
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238 | ushort t2_reference; /* timer 2 reference register */ |
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239 | ushort t2_capture; /* timer 2 capture register */ |
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240 | ushort t2_counter; /* timer 2 counter */ |
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241 | uchar tim_res3; /* reserved */ |
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242 | uchar t2_event; /* timer 2 event */ |
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243 | ushort tim_res4[3]; /* reserved */ |
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244 | |
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245 | /* command register */ |
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246 | |
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247 | uchar cp_cmd; /* communication processor command register */ |
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248 | uchar cp_cmd_res; /* reserved */ |
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249 | |
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250 | /* reserved */ |
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251 | |
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252 | uchar reserved_2[0x1e]; |
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253 | |
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254 | /* SCC registers */ |
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255 | |
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256 | struct scc_regs { |
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257 | ushort resvd; /* reserved */ |
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258 | ushort scon; /* SCC configuration register */ |
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259 | ushort scm; /* SCC mode register */ |
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260 | ushort dsr; /* SCC sync register */ |
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261 | uchar scce; /* SCC event register */ |
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262 | uchar res1; /* reserved */ |
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263 | uchar sccm; /* SCC mask register */ |
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264 | uchar res2; /* reserved */ |
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265 | uchar sccs; /* SCC status register */ |
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266 | uchar res3; /* reserved */ |
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267 | ushort res4; /* reserved */ |
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268 | } scc_regs[3]; |
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269 | |
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270 | /* SP (SCP + SMI) */ |
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271 | |
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272 | ushort scc_mode_reg; /* scp, smi mode + clock control */ |
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273 | |
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274 | /* Serial Interface */ |
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275 | |
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276 | ushort serial_int_mask; /* mask register */ |
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277 | ushort serial_int_mode; /* mode register */ |
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278 | |
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279 | /* reserved */ |
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280 | |
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281 | uchar reserved_3[0x74A]; |
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282 | |
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283 | |
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284 | |
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285 | /****************** 68 EN 302 specific registers **********************/ |
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286 | /** only available here if |
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287 | M68302_INTERNAL_RAM_BASE_ADD+0x1000=M68EN302_INTERNAL_RAM_BASE_ADD*/ |
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288 | |
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289 | /* Module Bus Control Registers */ |
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290 | |
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291 | ushort mbc; /* module bus control register MBC */ |
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292 | ushort ier; /* interrupt extension register IER */ |
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293 | ushort cser[4]; /* Chip Select extension registers CSERx */ |
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294 | ushort pcsr; /* parity control & status register PCSR */ |
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295 | |
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296 | ushort mbc_reserved; |
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297 | |
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298 | /* DRAM Controller Registers */ |
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299 | |
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300 | ushort dcr; /* DRAM Configuration register DCR */ |
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301 | ushort drfrsh; /* DRAM Refresh register DRFRSH */ |
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302 | ushort dba[2]; /* DRAM Bank Base Address Register */ |
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303 | |
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304 | uchar dram_reserved[0x7E8]; |
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305 | |
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306 | |
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307 | /* Ethernet Controller Registers */ |
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308 | |
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309 | ushort ecntrl; /* Ethernet Control Register */ |
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310 | ushort edma; /* Ethernet DMA Configuration Register */ |
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311 | ushort emrblr; /* Ethernet Max receive buffer length */ |
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312 | ushort intr_vect; /* Interruppt vector register */ |
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313 | ushort intr_event; /* Interruppt event register */ |
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314 | ushort intr_mask; /* Interruppt mask register */ |
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315 | ushort ecnfig; /* Ethernet Configuration */ |
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316 | ushort ether_test; /* Ethernet Test register */ |
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317 | ushort ar_cntrl; /* Address Recognition Control register */ |
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318 | |
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319 | uchar eth_reserved[0x1EE]; |
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320 | |
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321 | uchar cet[0x200]; /* CAM Entry Table */ |
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322 | struct m68302_scc_bd eth_bd[128]; /* Ethernet Buffer Descriptors Table */ |
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323 | |
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324 | }; |
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325 | |
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326 | #define M68302imp_ a_m68302_imp -> |
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327 | |
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328 | #define M68302imp_a_scc_bd_rx(scc,bd) \ |
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329 | (struct m68302_scc_bd FAR *)(&(M68302imp_ parm_ram[scc].scc_bd_rx[bd])) |
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330 | #define M68302imp_a_scc_bd_tx(scc,bd) \ |
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331 | (struct m68302_scc_bd FAR *)(&(M68302imp_ parm_ram[scc].scc_bd_tx[bd])) |
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332 | |
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333 | #define M68302imp_scc_rfcr(scc) (M68302imp_ parm_ram[scc].rfcr) |
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334 | #define M68302imp_scc_tfcr(scc) (M68302imp_ parm_ram[scc].tfcr) |
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335 | #define M68302imp_scc_mrblr(scc) (M68302imp_ parm_ram[scc].mrblr) |
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336 | #define M68302imp_scc_rbdn(scc) (M68302imp_ parm_ram[scc].rbdn) |
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337 | #define M68302imp_scc_tbdn(scc) (M68302imp_ parm_ram[scc].tbdn) |
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338 | |
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339 | #define M68302imp_a_scc_spp(scc) ((struct m68302_scc_spp FAR *)(M68302imp_ parm_ram[scc].scc_spp)) |
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340 | |
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341 | #define M68302imp_dma_res1 (M68302imp_ dma_res1) |
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342 | #define M68302imp_dma_mode (M68302imp_ dma_mode) |
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343 | #define M68302imp_dma_src (M68302imp_ dma_src) |
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344 | #define M68302imp_dma_dest (M68302imp_ dma_dest) |
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345 | #define M68302imp_dma_count (M68302imp_ dma_count) |
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346 | #define M68302imp_dma_status (M68302imp_ dma_status) |
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347 | #define M68302imp_dma_fct_code (M68302imp_ dma_fct_code) |
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348 | |
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349 | #define M68302imp_it_mode (M68302imp_ it_mode) |
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350 | #define M68302imp_it_pending (M68302imp_ it_pending) |
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351 | #define M68302imp_it_mask (M68302imp_ it_mask) |
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352 | #define M68302imp_it_inservice (M68302imp_ it_inservice) |
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353 | |
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354 | #define M68302imp_cs_base(i) (M68302imp_ cs[i].base) |
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355 | #define M68302imp_cs_option(i) (M68302imp_ cs[i].option) |
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356 | |
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357 | #define M68302imp_port_control(i) (M68302imp_ port[i].control) |
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358 | #define M68302imp_port_direction(i) (M68302imp_ port[i].direction) |
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359 | #define M68302imp_port_data(i) (M68302imp_ port[i].data) |
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360 | |
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361 | #define M68302imp_timer1_mode (M68302imp_ t1_mode) |
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362 | #define M68302imp_timer1_reference (M68302imp_ t1_reference) |
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363 | #define M68302imp_timer1_capture (M68302imp_ t1_capture) |
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364 | #define M68302imp_timer1_counter (M68302imp_ t1_counter) |
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365 | #define M68302imp_timer1_event (M68302imp_ t1_event) |
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366 | #define M68302imp_timer3_reference (M68302imp_ t3_reference) |
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367 | #define M68302imp_timer3_counter (M68302imp_ t3_counter) |
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368 | #define M68302imp_timer2_mode (M68302imp_ t2_mode) |
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369 | #define M68302imp_timer2_reference (M68302imp_ t2_reference) |
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370 | #define M68302imp_timer2_capture (M68302imp_ t2_capture) |
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371 | #define M68302imp_timer2_counter (M68302imp_ t2_counter) |
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372 | #define M68302imp_timer2_event (M68302imp_ t2_event) |
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373 | |
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374 | #define M68302imp_cp_cmd (M68302imp_ cp_cmd) |
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375 | |
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376 | #define M68302imp_scc_mode_reg (M68302imp_ scc_mode_reg) |
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377 | |
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378 | #define M68302imp_serial_int_mask (M68302imp_ serial_int_mask) |
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379 | #define M68302imp_serial_int_mode (M68302imp_ serial_int_mode) |
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380 | #define M68302imp_simask (M68302imp_serial_int_mask) |
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381 | #define M68302imp_simode (M68302imp_serial_int_mode) |
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382 | |
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383 | #define M68302imp_scon(i) (M68302imp_ scc_regs[i].scon) |
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384 | #define M68302imp_scm(i) (M68302imp_ scc_regs[i].scm) |
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385 | #define M68302imp_dsr(i) (M68302imp_ scc_regs[i].dsr) |
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386 | #define M68302imp_scce(i) (M68302imp_ scc_regs[i].scce) |
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387 | #define M68302imp_sccm(i) (M68302imp_ scc_regs[i].sccm) |
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388 | #define M68302imp_sccs(i) (M68302imp_ scc_regs[i].sccs) |
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389 | |
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390 | |
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391 | /*----------------------------------------------------------------------------*/ |
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392 | |
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393 | #define M68en302imp_mbc (M68302imp_ mbc) |
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394 | #define M68en302imp_ier (M68302imp_ ier) |
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395 | #define M68en302imp_cser(i) (M68302imp_ cser[i]) |
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396 | #define M68en302imp_pcsr (M68302imp_ pcsr) |
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397 | |
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398 | #define M68en302imp_dcr (M68302imp_ dcr) |
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399 | #define M68en302imp_drfrsh (M68302imp_ drfrsh) |
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400 | #define M68en302imp_dba(i) (M68302imp_ dba[i]) |
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401 | |
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402 | |
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403 | #define M68en302imp_ecntrl (M68302imp_ ecntrl) |
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404 | #define M68en302imp_edma (M68302imp_ edma) |
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405 | #define M68en302imp_emrblr (M68302imp_ emrblr) |
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406 | #define M68en302imp_intr_vect (M68302imp_ intr_vect) |
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407 | #define M68en302imp_intr_event (M68302imp_ intr_event) |
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408 | #define M68en302imp_intr_mask (M68302imp_ intr_mask) |
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409 | #define M68en302imp_ecnfig (M68302imp_ ecnfig) |
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410 | #define M68en302imp_ether_test (M68302imp_ ether_test) |
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411 | #define M68en302imp_ar_cntrl (M68302imp_ ar_cntrl) |
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412 | |
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413 | #define M68en302imp_cet (M68302imp_ cet) |
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414 | |
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415 | #define M68302imp_a_eth_bd(bd) \ |
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416 | (struct m68302_scc_bd *)(&(M68302imp_ eth_bd[bd])) |
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417 | |
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418 | /* PORTS */ |
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419 | |
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420 | #define PA0 0x0001 /* PORT A bit 0 */ |
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421 | #define PA1 0x0002 /* PORT A bit 1 */ |
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422 | #define PA2 0x0004 /* PORT A bit 2 */ |
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423 | #define PA3 0x0008 /* PORT A bit 3 */ |
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424 | #define PA4 0x0010 /* PORT A bit 4 */ |
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425 | #define PA5 0x0020 /* PORT A bit 5 */ |
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426 | #define PA6 0x0040 /* PORT A bit 6 */ |
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427 | #define PA7 0x0080 /* PORT A bit 7 */ |
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428 | #define PA8 0x0100 /* PORT A bit 8 */ |
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429 | #define PA9 0x0200 /* PORT A bit 9 */ |
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430 | #define PA10 0x0400 /* PORT A bit 10 */ |
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431 | #define PA11 0x0800 /* PORT A bit 11 */ |
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432 | #define PA12 0x1000 /* PORT A bit 12 */ |
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433 | #define PA13 0x2000 /* PORT A bit 13 */ |
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434 | #define PA14 0x4000 /* PORT A bit 14 */ |
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435 | #define PA15 0x8000 /* PORT A bit 15 */ |
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436 | |
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437 | #define PB0 0x0001 /* PORT B bit 0 */ |
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438 | #define PB1 0x0002 /* PORT B bit 1 */ |
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439 | #define PB2 0x0004 /* PORT B bit 2 */ |
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440 | #define PB3 0x0008 /* PORT B bit 3 */ |
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441 | #define PB4 0x0010 /* PORT B bit 4 */ |
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442 | #define PB5 0x0020 /* PORT B bit 5 */ |
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443 | #define PB6 0x0040 /* PORT B bit 6 */ |
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444 | #define PB7 0x0080 /* PORT B bit 7 */ |
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445 | #define PB8 0x0100 /* PORT B bit 8 */ |
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446 | #define PB9 0x0200 /* PORT B bit 9 */ |
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447 | #define PB10 0x0400 /* PORT B bit 10 */ |
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448 | |
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449 | #define PB11 0x0800 /* PORT B bit 11 */ |
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450 | |
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451 | /* MODULE BUS CONTROL (MBCTL) */ |
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452 | |
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453 | #define MBC_BCE 0x8000 |
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454 | #define MBC_MFC2 0x4000 |
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455 | #define MBC_MFC1 0x2000 |
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456 | #define MBC_MFC0 0x1000 |
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457 | #define MBC_BB 0x0800 |
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458 | #define MBC_PPE 0x0400 |
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459 | #define MBC_PM9 0x0200 |
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460 | #define MBC_PM8 0x0100 |
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461 | #define MBC_PM7 0x0080 |
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462 | #define MBC_PM6 0x0040 |
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463 | #define MBC_PM5 0x0020 |
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464 | #define MBC_PM4 0x0010 |
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465 | #define MBC_PM3 0x0008 |
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466 | #define MBC_PM2 0x0004 |
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467 | #define MBC_PM1 0x0002 |
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468 | #define MBC_PM0 0x0001 |
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469 | |
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470 | /* DRAM CONFIGURATION REG (DCR) */ |
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471 | |
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472 | #define DCR_SU0 0x0001 |
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473 | #define DCR_SU1 0x0002 |
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474 | #define DCR_WP0 0x0004 |
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475 | #define DCR_WP1 0x0008 |
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476 | #define DCR_W0 0x0010 |
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477 | #define DCR_W1 0x0020 |
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478 | #define DCR_P0 0x0040 |
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479 | #define DCR_P1 0x0080 |
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480 | #define DCR_PE0 0x0100 |
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481 | #define DCR_PE1 0x0200 |
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482 | #define DCR_E0 0x0400 |
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483 | #define DCR_E1 0x0800 |
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484 | |
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485 | /* M68302 INTERNAL RAM BASE ADDRESS INSTALLATION */ |
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486 | |
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487 | #define M68302_ram_base_add_install(base_reg_add,ram_base_add) \ |
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488 | do { \ |
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489 | *((ushort *)base_reg_add) = (ushort)(ram_base_add >> 12); \ |
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490 | a_m68302_imp = (struct m68302_imp *)ram_base_add; \ |
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491 | } while (0) |
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492 | |
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493 | #define M68302_system_ctrl_reg_install(val) (*((ulong *)M68302_SCR_ADD) = val) |
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494 | |
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495 | /* INTERRUPTION */ |
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496 | |
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497 | /* Interrupt mode selection */ |
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498 | |
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499 | #define M68302_it_mode_install(mode,vector_bank, \ |
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500 | extvect1,extvect6,extvect7,edgetrig1,edgetrig6,edgetrig7) \ |
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501 | M68302imp_it_mode = 0 | (mode << 15) | (vector_bank << 5) | \ |
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502 | (extvect7 << 14) | (extvect6 << 13) | (extvect1 <<12) | \ |
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503 | (edgetrig7 << 10) | (edgetrig6 << 9)|(edgetrig1 << 8) |
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504 | |
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505 | /* CHIP SELECTION */ |
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506 | |
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507 | /* 'read_write' support values : |
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508 | * |
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509 | * M68302_CS_READ_ONLY for read only memory access chip select |
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510 | * M68302_CS_READ_WRITE_ONLY for write only memory access chip select |
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511 | * M68302_CS_READ_AND_WRITE for read & write memory access chip select |
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512 | * |
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513 | * 'nb_wait_state' : number of wait-state(s) from 0 to 6, 7 for external |
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514 | * |
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515 | */ |
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516 | #define M68302_CS_READ_ONLY 0x02 /* read only memory access */ |
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517 | #define M68302_CS_WRITE_ONLY 0x22 /* write only memory access */ |
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518 | #define M68302_CS_READ_AND_WRITE 0x00 /* read and write memory access */ |
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519 | |
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520 | |
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521 | #define M68302_cs_install(cs_nb,base_add,range,nb_wait_state,read_write) \ |
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522 | do { \ |
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523 | M68302imp_cs_option(cs_nb) = (((~(range - 1)) >> 11) & 0x1FFC) | \ |
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524 | (nb_wait_state << 13) | (read_write & 0x2); \ |
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525 | M68302imp_cs_base(cs_nb) = (((base_add >> 11) & 0x1FFC) | \ |
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526 | ((read_write >> 4) & 0x2) | 1); \ |
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527 | } while (0) |
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528 | |
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529 | #define M68302_set_cs_br(base_add, read_write) \ |
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530 | ((((base_add) >> 11) & 0x1FFC) | (((read_write) >> 4) & 0x2) | 1) |
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531 | |
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532 | #define M68302_set_cs_or(range, nb_wait_state, read_write) \ |
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533 | ((((~(range - 1)) >> 11) & 0x1FFC) | \ |
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534 | ((nb_wait_state) << 13) | ((read_write) & 0x2)) |
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535 | |
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536 | #define M68302_get_cs_br(cs) \ |
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537 | (((ulong)((M68302imp_cs_base(cs)) & 0x1FFC)) << 11 ) |
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538 | |
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539 | /* DRAM */ |
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540 | |
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541 | #define M68en302_dram_install(bank,base_add,range) \ |
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542 | M68en302imp_dba (bank) = \ |
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543 | (((base_add >> 8) & 0xFE00) | (((~(range-1))>>16) & 0x007E) | 1) |
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544 | |
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545 | #endif |
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