source: rtems/c/src/lib/libbsp/m68k/gen68302/include/m302_int.h @ 66387986

4.104.114.84.95
Last change on this file since 66387986 was 8b868a11, checked in by Joel Sherrill <joel.sherrill@…>, on 12/14/00 at 17:53:53

2000-12-11 Joel Sherrill <joel@…>

  • Makefile.am, configure.in, include/Makefile.am, wrapup/Makefile.am: Updated to reflect addition of network driver by Franck Julien <FranckJ@…>.
  • include/m302_int.h, network/.cvsignore, network/Makefile.am, network/network.c: New file.
  • Property mode set to 100644
File size: 18.4 KB
Line 
1/*
2 *  Implements the Motorola 68302 multi-protocol chip parameter
3 *  definition header.
4 *
5 *  $Id$
6 */
7
8#ifndef __M302_INT_h
9#define __M302_INT_h
10
11#ifndef uchar
12#define uchar unsigned char
13#endif
14#ifndef ushort
15#define ushort unsigned short
16#endif
17#ifndef ulong
18#define ulong unsigned long
19#endif
20
21/* Ethernet Control Register ECNTRL */
22#define ECNTRL_BIT_RESET    0x0001
23#define ECNTRL_BIT_ETHER_EN  0x0002
24#define ECNTRL_BIT_GTS      0x0004
25
26/* Ethernet DMA Configuration Status Register EDMA */
27#define EDMA_BDERR_MASK      0xFE00
28
29#define EDMA_BDSIZE_MASK      0x00C0
30#define EDMA_BDSIZE_8T_120R    0x0000
31#define EDMA_BDSIZE_16T_112R  0x0040
32#define EDMA_BDSIZE_32T_96R    0x0080
33#define EDMA_BDSIZE_64T_64R    0x00C0
34
35#define EDMA_BIT_TSRLY      0x0020
36
37#define EDMA_WMRK_MASK      0x0018
38#define EDMA_WMRK_8FIFO      0x0000
39#define EDMA_WMRK_16FIFO    0x0008
40#define EDMA_WMRK_24FIFO    0x0010
41#define EDMA_WMRK_32FIFO    0x0018
42
43#define EDMA_BLIM_MASK      0x0007
44#define EDMA_BLIM_8ACCESS    0x0003
45
46
47/* Ethernet Maximum Receive Buffer Length EMRBLR */
48#define EMRBLR_MASK          0x07FFE
49
50/* Interrupt Vector Register IVEC */
51#define IVEC_BIT_VG          0x0100
52#define IVEC_INV_MASK        0x00FF
53
54/* Interrupt Event Register INTR_EVENT */
55#define INTR_EVENT_BIT_RXB      0x0001
56#define INTR_EVENT_BIT_TXB      0x0002
57#define INTR_EVENT_BIT_BSY      0x0004
58#define INTR_EVENT_BIT_RFINT    0x0008
59#define INTR_EVENT_BIT_TFINT    0x0010
60#define INTR_EVENT_BIT_EBERR    0x0020
61#define INTR_EVENT_BIT_BOD      0x0040
62#define INTR_EVENT_BIT_GRA      0x0080
63#define INTR_EVENT_BIT_BABT      0x0100
64#define INTR_EVENT_BIT_BABR      0x0200
65#define INTR_EVENT_BIT_HBERR    0x0400
66
67/* Interrupt Mask Register INTR_MASK */
68#define INTR_MASK_BIT_RXIEN      0x0001
69#define INTR_MASK_BIT_TXIEN      0x0002
70#define INTR_MASK_BIT_BSYEN      0x0004
71#define INTR_MASK_BIT_RFIEN      0x0008
72#define INTR_MASK_BIT_TFIEN      0x0010
73#define INTR_MASK_BIT_EBERREN    0x0020
74#define INTR_MASK_BIT_BODEN      0x0040
75#define INTR_MASK_BIT_GRAEN      0x0080
76#define INTR_MASK_BIT_BTEN      0x0100
77#define INTR_MASK_BIT_BREN      0x0200
78#define INTR_MASK_BIT_HBEEN      0x0400
79
80/* Ethernet Configuration ECNFIG */
81#define ECNFIG_BIT_LOOP          0x0001
82#define ECNFIG_BIT_FDEN          0x0002
83#define ECNFIG_BIT_HBC          0x0004
84#define ECNFIG_BIT_RDT          0x0008
85
86/* Ethernet Test ETHER_TEST */
87#define ETHER_TEST_BIT_TWS      0x0001
88#define ETHER_TEST_BIT_RWS      0x0002
89#define ETHER_TEST_BIT_DRTY      0x0004
90#define ETHER_TEST_BIT_COLL      0x0008
91#define ETHER_TEST_BIT_SLOT      0x0010
92#define ETHER_TEST_BIT_TRND      0x0020
93#define ETHER_TEST_BIT_TBO      0x0040
94#define ETHER_TEST_BIT_RNGT      0x0080
95#define ETHER_TEST_REV_MASK      0xF000
96
97/* Ethernet AR Control Registere AR_CNTRL */
98#define AR_CNTRL_BIT_PROM        0x0400
99#define AR_CNTRL_BIT_PA_REJ      0x0800
100#define AR_CNTRL_BIT_NO_BROADCAST  0x1000
101#define AR_CNTRL_BIT_MULTI1      0x2000
102#define AR_CNTRL_BIT_INDEX_EN    0x4000
103#define AR_CNTRL_BIT_HASH_EN    0x8000
104
105#define AR_CNTRL_MULTI_MASK      (AR_CNTRL_BIT_MULTI0 | AR_CNTRL_BIT_MULTI1)
106
107
108/* Ethernet buffer Status TX */
109#define BUF_STAT_CARRIER_LOST    0x0001
110#define BUF_STAT_UNDERRUN        0x0002
111#define BUF_STAT_RETRANS_COUNT  0x003C
112#define BUF_STAT_RETRY_LIMIT    0x0040
113#define BUF_STAT_LATE_COLLISION  0x0080
114#define BUF_STAT_HEARTBIT        0x0100
115#define BUF_STAT_DEFER          0x0200
116#define BUF_STAT_TX_CRC          0x0400
117#define BUF_STAT_LAST            0x0800
118#define BUF_STAT_INTERRUPT      0x1000
119#define BUF_STAT_WRAP            0x2000
120#define BUF_STAT_TO              0x4000
121#define BUF_STAT_READY          0x8000
122
123
124/* Ethernet buffer Status RX */
125#define BUF_STAT_COLLISION      0x0001
126#define BUF_STAT_OVERRUN        0x0002
127#define BUF_STAT_CRC_ERROR      0x0004
128#define BUF_STAT_SHORT          0x0008
129#define BUF_STAT_NONALIGNED      0x0010
130#define BUF_STAT_LONG            0x0020
131#define BUF_STAT_FIRST_IN_FRAME  0x0400
132#define BUF_STAT_EMPTY          0x8000
133
134  /* SCC Buffer Descriptor structure
135  ----------------------------------*/
136
137struct m68302_scc_bd {
138  ushort      stat_ctrl;
139  ushort      data_lgth;
140  uchar      *p_buffer;
141};
142
143#define M68302_scc_bd_stat_ctrl(p) \
144    (((struct m68302_scc_bd *)(p)) -> stat_ctrl)
145#define M68302_scc_bd_data_lgth(p) \
146    (((struct m68302_scc_bd *)(p)) -> data_lgth)
147#define M68302_scc_bd_p_buffer(p)  \
148   (((struct m68302_scc_bd *)(p)) -> p_buffer)
149
150struct m68302_imp {
151
152/* BASE : user data memory  */
153
154  uchar  user_data[0x240];        /* 0x240 bytes user data */
155  uchar  user_reserved[0x1c0];    /* empty till 0x400 */
156
157/* BASE + 400H: PARAMETER RAM */
158  struct {
159    struct m68302_scc_bd scc_bd_rx[8];  /* Rx buffer descriptors */
160    struct m68302_scc_bd scc_bd_tx[8];  /* Tx buffer descriptors */
161
162    uchar      rfcr;        /* Rx function code */
163    uchar      tfcr;        /* Tx function code */
164    ushort     mrblr;        /* maximum Rx buffer length */
165    ushort     rist;        /* internal state */
166    uchar      res1;
167    uchar      rbdn;        /* Rx internal buffer number */
168    ulong      ridp;
169    ushort     ribc;
170    ushort     rtmp;
171    ushort     tist;
172    uchar      res2;
173    uchar      tbdn;        /* Tx internal buffer number */
174    ulong      tidp;
175    ushort     tibc;
176    ushort     ttmp;
177
178    unsigned char  scc_spp  [0x64];    /* SCC specific parameters */
179  } parm_ram [3];
180
181  uchar reserved_1 [0x100];
182
183/* BASE + 800H: INTERNAL REGISTERS */
184
185    /* DMA */
186
187  ushort  dma_res1;           /* reserved */
188  ushort  dma_mode;           /* dma mode reg */
189  ulong   dma_src;            /* dma source */
190  ulong   dma_dest;           /* dma destination */
191  ushort  dma_count;          /* dma byte count */
192  uchar   dma_status;         /* dma status */
193  uchar   dma_res2;           /* reserved */
194  uchar   dma_fct_code;       /* dma function code */
195  uchar   dma_res3;           /* reserved */
196
197    /* Interrupt Controller */
198
199  ushort  it_mode;            /* interrupt mode register */
200  ushort  it_pending;         /* interrupt pending register */
201  ushort  it_mask;            /* interrupt mask register */
202  ushort  it_inservice;       /* interrupt in service register */
203  ulong   it_reserved;        /* reserved */
204
205    /* Parallel I/O */
206
207  struct {
208    ushort  control;         /* port control register */
209    ushort  direction;       /* port data direction register */
210    ushort  data;            /* port data value register */
211  } port[2];
212
213  ushort  p_reserved;        /* reserved */
214
215    /* Chip Select */
216
217  ulong  cs_reserved;
218
219  struct {
220    ushort  base;            /* chip select base register */
221    ushort  option;          /* chip select option register */
222  } cs[4];
223
224    /* Timer */
225
226  ushort  t1_mode;             /* timer 1 mode register */
227  ushort  t1_reference;        /* timer 1 reference register */
228  ushort  t1_capture;          /* timer 1 capture register */
229  ushort  t1_counter;          /* timer 1 counter */
230  uchar   tim_res1;            /* reserved */
231  uchar   t1_event;            /* timer 1 event */
232
233  ushort  t3_reference;        /* timer 3 reference register */
234  ushort  t3_counter;          /* timer 3 counter */
235  ushort  tim_res2;            /* reserved */
236
237  ushort  t2_mode;              /* timer 2 mode register */
238  ushort  t2_reference;         /* timer 2 reference register */
239  ushort  t2_capture;           /* timer 2 capture register */
240  ushort  t2_counter;           /* timer 2 counter */
241  uchar   tim_res3;             /* reserved */
242  uchar   t2_event;             /* timer 2 event */
243  ushort  tim_res4[3];          /* reserved */
244
245    /* command register */
246
247  uchar  cp_cmd;                /* communication processor command register */
248  uchar  cp_cmd_res;            /* reserved */
249
250    /* reserved */
251
252  uchar  reserved_2[0x1e];
253
254    /* SCC registers */
255
256  struct scc_regs {
257    ushort  resvd;           /* reserved */
258    ushort  scon;            /* SCC configuration register */
259    ushort  scm;             /* SCC mode register */
260    ushort  dsr;             /* SCC sync register */
261    uchar   scce;            /* SCC event register */
262    uchar   res1;            /* reserved */
263    uchar   sccm;            /* SCC mask register */
264    uchar   res2;            /* reserved */
265    uchar   sccs;            /* SCC status register */
266    uchar   res3;            /* reserved */
267    ushort  res4;            /* reserved */
268  } scc_regs[3];
269
270    /* SP (SCP + SMI) */
271
272  ushort  scc_mode_reg;          /* scp, smi mode + clock control */
273
274    /* Serial Interface */
275
276  ushort  serial_int_mask;        /* mask register */
277  ushort  serial_int_mode;        /* mode register */
278
279    /* reserved */
280
281  uchar  reserved_3[0x74A];
282
283
284
285/****************** 68 EN 302 specific registers **********************/
286/** only available here if
287    M68302_INTERNAL_RAM_BASE_ADD+0x1000=M68EN302_INTERNAL_RAM_BASE_ADD*/
288
289    /* Module Bus Control Registers */
290
291  ushort  mbc;              /* module bus control register MBC */
292  ushort  ier;              /* interrupt extension register IER */
293  ushort  cser[4];          /* Chip Select extension registers CSERx */
294  ushort  pcsr;             /* parity control & status register PCSR */
295
296  ushort  mbc_reserved;
297
298    /* DRAM Controller Registers */
299
300  ushort  dcr;              /* DRAM Configuration register DCR */
301  ushort  drfrsh;           /* DRAM Refresh register DRFRSH */
302  ushort  dba[2];           /* DRAM Bank Base Address Register */
303
304  uchar  dram_reserved[0x7E8];
305
306
307    /* Ethernet Controller Registers */
308
309  ushort  ecntrl;            /* Ethernet Control Register */
310  ushort  edma;              /* Ethernet DMA Configuration Register */
311  ushort  emrblr;            /* Ethernet Max receive buffer length */
312  ushort  intr_vect;         /* Interruppt vector register */
313  ushort  intr_event;        /* Interruppt event register */
314  ushort  intr_mask;         /* Interruppt mask register */
315  ushort  ecnfig;            /* Ethernet Configuration */
316  ushort  ether_test;        /* Ethernet Test register */
317  ushort  ar_cntrl;          /* Address Recognition Control register */
318
319  uchar  eth_reserved[0x1EE];
320
321  uchar  cet[0x200];                  /* CAM Entry Table */
322  struct m68302_scc_bd eth_bd[128];   /* Ethernet Buffer Descriptors Table */
323
324};
325
326#define M68302imp_     a_m68302_imp ->
327
328#define M68302imp_a_scc_bd_rx(scc,bd) \
329     (struct m68302_scc_bd FAR *)(&(M68302imp_ parm_ram[scc].scc_bd_rx[bd]))
330#define M68302imp_a_scc_bd_tx(scc,bd) \
331     (struct m68302_scc_bd FAR *)(&(M68302imp_ parm_ram[scc].scc_bd_tx[bd]))
332
333#define M68302imp_scc_rfcr(scc)      (M68302imp_ parm_ram[scc].rfcr)
334#define M68302imp_scc_tfcr(scc)      (M68302imp_ parm_ram[scc].tfcr)
335#define M68302imp_scc_mrblr(scc)     (M68302imp_ parm_ram[scc].mrblr)
336#define M68302imp_scc_rbdn(scc)      (M68302imp_ parm_ram[scc].rbdn)
337#define M68302imp_scc_tbdn(scc)      (M68302imp_ parm_ram[scc].tbdn)
338
339#define M68302imp_a_scc_spp(scc)    ((struct m68302_scc_spp FAR *)(M68302imp_ parm_ram[scc].scc_spp))
340
341#define M68302imp_dma_res1        (M68302imp_ dma_res1)
342#define M68302imp_dma_mode        (M68302imp_ dma_mode)
343#define M68302imp_dma_src         (M68302imp_ dma_src)
344#define M68302imp_dma_dest        (M68302imp_ dma_dest)
345#define M68302imp_dma_count       (M68302imp_ dma_count)
346#define M68302imp_dma_status      (M68302imp_ dma_status)
347#define M68302imp_dma_fct_code    (M68302imp_ dma_fct_code)
348
349#define M68302imp_it_mode         (M68302imp_ it_mode)
350#define M68302imp_it_pending      (M68302imp_ it_pending)
351#define M68302imp_it_mask         (M68302imp_ it_mask)
352#define M68302imp_it_inservice    (M68302imp_ it_inservice)
353
354#define M68302imp_cs_base(i)      (M68302imp_ cs[i].base)
355#define M68302imp_cs_option(i)    (M68302imp_ cs[i].option)
356
357#define M68302imp_port_control(i)    (M68302imp_ port[i].control)
358#define M68302imp_port_direction(i)  (M68302imp_ port[i].direction)
359#define M68302imp_port_data(i)       (M68302imp_ port[i].data)
360
361#define M68302imp_timer1_mode        (M68302imp_ t1_mode)
362#define M68302imp_timer1_reference   (M68302imp_ t1_reference)
363#define M68302imp_timer1_capture     (M68302imp_ t1_capture)
364#define M68302imp_timer1_counter     (M68302imp_ t1_counter)
365#define M68302imp_timer1_event       (M68302imp_ t1_event)
366#define M68302imp_timer3_reference   (M68302imp_ t3_reference)
367#define M68302imp_timer3_counter     (M68302imp_ t3_counter)
368#define M68302imp_timer2_mode        (M68302imp_ t2_mode)
369#define M68302imp_timer2_reference   (M68302imp_ t2_reference)
370#define M68302imp_timer2_capture     (M68302imp_ t2_capture)
371#define M68302imp_timer2_counter     (M68302imp_ t2_counter)
372#define M68302imp_timer2_event       (M68302imp_ t2_event)
373
374#define M68302imp_cp_cmd             (M68302imp_ cp_cmd)
375
376#define M68302imp_scc_mode_reg       (M68302imp_ scc_mode_reg)
377
378#define M68302imp_serial_int_mask    (M68302imp_ serial_int_mask)
379#define M68302imp_serial_int_mode    (M68302imp_ serial_int_mode)
380#define M68302imp_simask             (M68302imp_serial_int_mask)
381#define M68302imp_simode             (M68302imp_serial_int_mode)
382
383#define M68302imp_scon(i)            (M68302imp_ scc_regs[i].scon)
384#define M68302imp_scm(i)             (M68302imp_ scc_regs[i].scm)
385#define M68302imp_dsr(i)             (M68302imp_ scc_regs[i].dsr)
386#define M68302imp_scce(i)            (M68302imp_ scc_regs[i].scce)
387#define M68302imp_sccm(i)            (M68302imp_ scc_regs[i].sccm)
388#define M68302imp_sccs(i)            (M68302imp_ scc_regs[i].sccs)
389
390
391/*----------------------------------------------------------------------------*/
392
393#define M68en302imp_mbc              (M68302imp_ mbc)
394#define M68en302imp_ier              (M68302imp_ ier)
395#define M68en302imp_cser(i)          (M68302imp_ cser[i])
396#define M68en302imp_pcsr             (M68302imp_ pcsr)
397
398#define M68en302imp_dcr              (M68302imp_ dcr)
399#define M68en302imp_drfrsh           (M68302imp_ drfrsh)
400#define M68en302imp_dba(i)           (M68302imp_ dba[i])
401
402
403#define M68en302imp_ecntrl           (M68302imp_ ecntrl)
404#define M68en302imp_edma             (M68302imp_ edma)
405#define M68en302imp_emrblr           (M68302imp_ emrblr)
406#define M68en302imp_intr_vect        (M68302imp_ intr_vect)
407#define M68en302imp_intr_event       (M68302imp_ intr_event)
408#define M68en302imp_intr_mask        (M68302imp_ intr_mask)
409#define M68en302imp_ecnfig           (M68302imp_ ecnfig)
410#define M68en302imp_ether_test       (M68302imp_ ether_test)
411#define M68en302imp_ar_cntrl         (M68302imp_ ar_cntrl)
412
413#define M68en302imp_cet              (M68302imp_ cet)
414
415#define M68302imp_a_eth_bd(bd) \
416    (struct m68302_scc_bd *)(&(M68302imp_ eth_bd[bd]))
417
418/* PORTS */
419
420#define PA0     0x0001    /* PORT A bit 0 */
421#define PA1     0x0002    /* PORT A bit 1 */
422#define PA2     0x0004    /* PORT A bit 2 */
423#define PA3     0x0008    /* PORT A bit 3 */
424#define PA4     0x0010    /* PORT A bit 4 */
425#define PA5     0x0020    /* PORT A bit 5 */
426#define PA6     0x0040    /* PORT A bit 6 */
427#define PA7     0x0080    /* PORT A bit 7 */
428#define PA8     0x0100    /* PORT A bit 8 */
429#define PA9     0x0200    /* PORT A bit 9 */
430#define PA10    0x0400    /* PORT A bit 10 */
431#define PA11    0x0800    /* PORT A bit 11 */
432#define PA12    0x1000    /* PORT A bit 12 */
433#define PA13    0x2000    /* PORT A bit 13 */
434#define PA14    0x4000    /* PORT A bit 14 */
435#define PA15    0x8000    /* PORT A bit 15 */
436
437#define PB0     0x0001    /* PORT B bit 0 */
438#define PB1     0x0002    /* PORT B bit 1 */
439#define PB2     0x0004    /* PORT B bit 2 */
440#define PB3     0x0008    /* PORT B bit 3 */
441#define PB4     0x0010    /* PORT B bit 4 */
442#define PB5     0x0020    /* PORT B bit 5 */
443#define PB6     0x0040    /* PORT B bit 6 */
444#define PB7     0x0080    /* PORT B bit 7 */
445#define PB8     0x0100    /* PORT B bit 8 */
446#define PB9     0x0200    /* PORT B bit 9 */
447#define PB10    0x0400    /* PORT B bit 10 */
448
449#define PB11    0x0800    /* PORT B bit 11 */
450
451/* MODULE BUS CONTROL (MBCTL) */
452
453#define MBC_BCE   0x8000
454#define MBC_MFC2  0x4000
455#define MBC_MFC1  0x2000
456#define MBC_MFC0  0x1000
457#define MBC_BB    0x0800
458#define MBC_PPE   0x0400
459#define MBC_PM9   0x0200
460#define MBC_PM8   0x0100
461#define MBC_PM7   0x0080
462#define MBC_PM6   0x0040
463#define MBC_PM5   0x0020
464#define MBC_PM4   0x0010
465#define MBC_PM3   0x0008
466#define MBC_PM2   0x0004
467#define MBC_PM1   0x0002
468#define MBC_PM0   0x0001
469
470  /* DRAM CONFIGURATION REG (DCR) */
471
472#define DCR_SU0   0x0001
473#define DCR_SU1   0x0002
474#define DCR_WP0   0x0004
475#define DCR_WP1   0x0008
476#define DCR_W0    0x0010
477#define DCR_W1    0x0020
478#define DCR_P0    0x0040
479#define DCR_P1    0x0080
480#define DCR_PE0   0x0100
481#define DCR_PE1   0x0200
482#define DCR_E0    0x0400
483#define DCR_E1    0x0800
484
485/* M68302 INTERNAL RAM BASE ADDRESS INSTALLATION */
486
487#define M68302_ram_base_add_install(base_reg_add,ram_base_add) \
488  do { \
489    *((ushort *)base_reg_add) =  (ushort)(ram_base_add >> 12); \
490   a_m68302_imp = (struct m68302_imp *)ram_base_add; \
491  } while (0)
492
493#define M68302_system_ctrl_reg_install(val) (*((ulong *)M68302_SCR_ADD) = val)
494
495  /* INTERRUPTION */
496
497  /* Interrupt mode selection */
498
499#define M68302_it_mode_install(mode,vector_bank, \
500  extvect1,extvect6,extvect7,edgetrig1,edgetrig6,edgetrig7) \
501    M68302imp_it_mode = 0 | (mode << 15) | (vector_bank << 5) | \
502        (extvect7 << 14) | (extvect6 << 13) | (extvect1 <<12) | \
503        (edgetrig7 << 10) | (edgetrig6 << 9)|(edgetrig1 << 8)
504
505  /* CHIP SELECTION */
506
507  /* 'read_write' support values :
508   *
509   *  M68302_CS_READ_ONLY      for read only memory access chip select
510   *  M68302_CS_READ_WRITE_ONLY  for write only memory access chip select
511   *  M68302_CS_READ_AND_WRITE  for read & write memory access chip select
512   *
513   *  'nb_wait_state' : number of wait-state(s) from 0 to 6, 7 for external
514   *
515   */
516#define M68302_CS_READ_ONLY      0x02 /* read only memory access */
517#define M68302_CS_WRITE_ONLY     0x22 /* write only memory access */
518#define M68302_CS_READ_AND_WRITE 0x00 /* read and write memory access */
519
520
521#define M68302_cs_install(cs_nb,base_add,range,nb_wait_state,read_write) \
522  do { \
523    M68302imp_cs_option(cs_nb) = (((~(range - 1)) >> 11) & 0x1FFC) | \
524      (nb_wait_state << 13) | (read_write & 0x2); \
525    M68302imp_cs_base(cs_nb) = (((base_add >> 11) & 0x1FFC) | \
526      ((read_write >> 4) & 0x2) | 1); \
527  } while (0)
528
529#define M68302_set_cs_br(base_add, read_write)  \
530    ((((base_add) >> 11) & 0x1FFC) | (((read_write) >> 4) & 0x2) | 1)
531
532#define M68302_set_cs_or(range, nb_wait_state, read_write) \
533   ((((~(range - 1)) >> 11) & 0x1FFC) | \
534       ((nb_wait_state) << 13) | ((read_write) & 0x2))
535
536#define M68302_get_cs_br(cs)  \
537    (((ulong)((M68302imp_cs_base(cs)) & 0x1FFC)) << 11 )
538
539/* DRAM */
540
541#define M68en302_dram_install(bank,base_add,range)  \
542  M68en302imp_dba (bank)  = \
543    (((base_add >> 8) & 0xFE00) | (((~(range-1))>>16) & 0x007E) | 1)
544
545#endif
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