1 | /* |
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2 | *------------------------------------------------------------------- |
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3 | * |
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4 | * This file contains the subroutines necessary to initalize |
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5 | * the DP8750A TCP on the efi68k board. |
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6 | * |
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7 | * This file has been created by John S. Gwynne for the efi68k |
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8 | * project. |
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9 | * |
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10 | * The license and distribution terms for this file may in |
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11 | * the file LICENSE in this distribution or at |
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12 | * http://www.OARcorp.com/rtems/license.html. |
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13 | * |
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14 | *------------------------------------------------------------------ |
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15 | * |
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16 | * $Id$ |
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17 | */ |
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18 | |
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19 | #include <bsp.h> |
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20 | |
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21 | /* define tcp struct pointers */ |
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22 | struct clock_ram * const tcp_power_up = |
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23 | (struct clock_ram * const)(0x16*2+TCP_BASE_ADDRESS); |
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24 | |
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25 | struct clock_ram * const tcp_power_down = |
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26 | (struct clock_ram * const)(0x1b*2+TCP_BASE_ADDRESS); |
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27 | |
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28 | struct clock_counters * const tcp_clock = |
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29 | (struct clock_counters * const)(0x05*2+TCP_BASE_ADDRESS); |
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30 | |
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31 | struct clock_ram * const tcp_save_ram = |
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32 | (struct clock_ram * const)(0x19*2+TCP_BASE_ADDRESS); |
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33 | |
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34 | #define X_DELAY 300 /* time-out delay for crystal start */ |
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35 | #define X1_DELAY 100000 |
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36 | |
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37 | void tcp_delay(int count) |
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38 | { |
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39 | int i; |
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40 | /* change latter to use a counter !!! */ |
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41 | for (i=0;i<count/4;i++); |
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42 | } |
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43 | |
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44 | void tcp_init() |
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45 | { |
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46 | unsigned char low_bat, osc_fail, power_up; |
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47 | unsigned char mon, dom, hrs, min, sec; |
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48 | int i, count; |
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49 | |
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50 | /* delay about 60us to ensure TCP is not locked-out */ |
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51 | tcp_delay(80); |
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52 | |
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53 | /* set normal supply mode and reset test mode bit */ |
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54 | *MSR = 0; |
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55 | *PFR = 0; |
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56 | |
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57 | /* save oscillator failure condition */ |
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58 | *MSR = 0; /* set RS and PS to zero */ |
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59 | osc_fail = (*PFR & OSF ? 1 : 0); |
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60 | *MSR = PS; |
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61 | *RAM_OSC_FAIL = *RAM_OSC_FAIL || osc_fail; |
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62 | |
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63 | *MSR = PS; |
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64 | if (*RAM_OSC_FAIL) { |
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65 | power_up = 1; |
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66 | *MSR = PS; |
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67 | *RAM_POWERUP = power_up; |
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68 | /* clear time counters and power up & down ram */ |
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69 | *MSR = 0; |
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70 | tcp_clock->hofs = 0; |
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71 | tcp_clock->sec = 0; |
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72 | tcp_clock->min = 0; |
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73 | tcp_clock->hrs = 0; |
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74 | tcp_clock->dom = 1; |
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75 | tcp_clock->mon = 1; |
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76 | tcp_clock->yr = 0x95; |
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77 | tcp_clock->jd0 = 0x01; |
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78 | tcp_clock->jd1 = 0; |
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79 | tcp_clock->dow = 1; |
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80 | *MSR = PS; |
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81 | tcp_power_up->sec = 0; |
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82 | tcp_power_up->min = 0; |
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83 | tcp_power_up->hrs = 0; |
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84 | tcp_power_up->dom = 0; |
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85 | tcp_power_up->mon = 0; |
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86 | tcp_power_down->sec = 0; |
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87 | tcp_power_down->min = 0; |
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88 | tcp_power_down->hrs = 0; |
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89 | tcp_power_down->dom = 0; |
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90 | tcp_power_down->mon = 0; |
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91 | } else { |
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92 | /* save for power-up test */ |
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93 | *MSR = 0; |
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94 | power_up = (*IRR & TMSE ? 0 : 1); |
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95 | *MSR = PS; |
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96 | *RAM_POWERUP = power_up; |
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97 | |
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98 | /* update tcp_power_up and tcp_power_down on power up */ |
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99 | if (power_up) { |
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100 | *MSR = 0; |
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101 | do { |
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102 | *PFR; |
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103 | sec = tcp_clock->sec; |
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104 | min = tcp_clock->min; |
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105 | hrs = tcp_clock->hrs; |
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106 | dom = tcp_clock->dom; |
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107 | mon = tcp_clock->mon; |
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108 | } while (*PFR & R_1S); |
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109 | *MSR = PS; |
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110 | tcp_power_up->sec = sec; |
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111 | tcp_power_up->min = min; |
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112 | tcp_power_up->hrs = hrs; |
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113 | tcp_power_up->dom = dom; |
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114 | tcp_power_up->mon = ( (((mon>>4)*10)+(mon&0xf))>12 ? 0 : mon ); |
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115 | *MSR = 0; /* save ram is not running */ |
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116 | sec = tcp_save_ram->sec; |
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117 | min = tcp_save_ram->min; |
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118 | hrs = tcp_save_ram->hrs; |
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119 | dom = tcp_save_ram->dom; |
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120 | mon = tcp_save_ram->mon; |
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121 | *MSR = PS; |
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122 | tcp_power_down->sec = sec; |
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123 | tcp_power_down->min = min; |
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124 | tcp_power_down->hrs = hrs; |
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125 | tcp_power_down->dom = dom; |
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126 | tcp_power_down->mon = ( (((mon>>4)*10)+(mon&0xf))>12 ? 0 : mon ); |
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127 | } |
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128 | } |
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129 | |
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130 | /* load interrupt routing reg. PF must be enabled to test |
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131 | for low battery, but I route it to MFO to avoid any |
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132 | potential problems */ |
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133 | *MSR = 0; |
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134 | *IRR = PF_R | TMSE; |
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135 | |
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136 | /* initialize the output mode register */ |
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137 | *MSR = RS; |
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138 | *OMR = IP | MP | MO; /* INTR active low and push/pull */ |
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139 | |
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140 | /* initialize interrupt control reg 0 */ |
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141 | *MSR = RS; |
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142 | *ICR0 = 0; /* disable all interrupts */ |
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143 | |
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144 | /* initialize interrupt control reg 1 */ |
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145 | *MSR = RS; |
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146 | *ICR1 = PFE; /* this also enables the low battery |
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147 | detection circuit. */ |
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148 | |
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149 | /* I had trouble getting the tcp to be completely |
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150 | flexible to supply modes (i.e., automatically |
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151 | selecting single or normal battery backup modes based |
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152 | on inputs at power-up. If single supply mode is |
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153 | selected, the low battery detect is disabled and the |
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154 | low battery detect in normal mode does not seem to |
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155 | detect when no battery is present at all. If normal |
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156 | mode is selected and no battery is present, the |
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157 | crystal will stop, but only if reset after |
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158 | power-up. It would seem that after a power-up reset, |
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159 | with no battery, the chip may automaticlly switch to |
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160 | single supply mode which disables the low battery |
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161 | detection circuit.) The following software tests |
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162 | works for all permiatations of low batt, reset, |
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163 | power-on reset, battery, no battery, battery on after |
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164 | Vcc,.... *except* for battery switched on for the |
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165 | first time before power up in which case the chip |
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166 | will still be in single suppy mode till restarted (a |
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167 | second call to tcp_init such as when the time is set |
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168 | or a reboot.) The timer/clock itself should always |
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169 | be completely functional regardless of the supply |
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170 | mode. */ |
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171 | |
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172 | |
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173 | /* initialize the real time mode register */ |
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174 | /* note: write mode bits *before* CSS, then set CSS */ |
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175 | *MSR = 0; /* clear roll-over */ |
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176 | *PFR; |
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177 | count=1; |
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178 | for (i=0;i<X_DELAY;i++) { /* loop till xtal starts */ |
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179 | *MSR = RS; |
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180 | *RTMR = (*RTMR & (LY0 | LY1 )) | CSS; |
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181 | *MSR = 0; |
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182 | if (*PFR & R_1MS) |
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183 | if (!(count--)) break; |
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184 | } |
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185 | if (i>=X_DELAY) { |
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186 | { |
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187 | /* xtal didn't start; try single supply mode */ |
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188 | *MSR = 0; /* single supply */ |
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189 | *PFR = OSF; |
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190 | *MSR = 0; /* clear roll-over */ |
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191 | *PFR; |
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192 | count=1; |
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193 | for (i=0;i<X1_DELAY;i++) { /* loop till xtal starts */ |
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194 | *MSR = RS; |
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195 | *RTMR = (*RTMR & (LY0 | LY1 )) | CSS; |
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196 | *MSR = 0; |
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197 | if (*PFR & R_1MS) |
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198 | if (!(count--)) break; |
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199 | } |
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200 | if (i>=X1_DELAY) { |
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201 | /* xtal didn't start; fail tcp */ |
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202 | *MSR = PS; |
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203 | *RAM_TCP_FAILURE = 1; |
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204 | *MSR = PS; |
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205 | *RAM_SINGLE_SUP=1; |
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206 | } else { |
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207 | *MSR = PS; |
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208 | *RAM_TCP_FAILURE = 0; |
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209 | *MSR = PS; |
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210 | *RAM_SINGLE_SUP=1; |
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211 | } |
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212 | } |
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213 | } else { |
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214 | *MSR = PS; |
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215 | *RAM_TCP_FAILURE = 0; |
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216 | *MSR = PS; |
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217 | *RAM_SINGLE_SUP=0; |
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218 | } |
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219 | |
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220 | /* wait for low battery detection circuit to stabalize */ |
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221 | tcp_delay(1000); |
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222 | |
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223 | /* battery test */ |
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224 | *MSR = 0; |
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225 | low_bat = (*IRR & LBF ? 1 : 0 ); |
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226 | *MSR = PS; |
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227 | *RAM_LOWBAT = low_bat & !(*RAM_SINGLE_SUP); |
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228 | |
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229 | /* reset pending interrupts */ |
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230 | *MSR = ( PER | AL | T0 | T1 ); |
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231 | |
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232 | /* resync the time save ram with the clock */ |
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233 | tcp_save_ram->sec = 0; |
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234 | tcp_save_ram->min = 0; |
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235 | tcp_save_ram->hrs = 0; |
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236 | tcp_save_ram->dom = 0; |
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237 | tcp_save_ram->mon = 0; |
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238 | } |
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