source: rtems/c/src/lib/libbsp/m68k/efi68k/startup/efi68k_tcp.c @ 7d74395f

4.104.114.84.95
Last change on this file since 7d74395f was 7d74395f, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 18, 1996 at 4:43:12 PM

corrected typo

  • Property mode set to 100644
File size: 6.9 KB
Line 
1/*
2 *-------------------------------------------------------------------
3 *
4 * This file contains the subroutines necessary to initalize
5 * the DP8750A TCP on the efi68k board.
6 *
7 * This file has been created by John S. Gwynne for the efi68k
8 * project.
9 *
10 * Redistribution and use in source and binary forms are permitted
11 * provided that the following conditions are met:
12 * 1. Redistribution of source code and documentation must retain
13 *    the above authorship, this list of conditions and the
14 *    following disclaimer.
15 * 2. The name of the author may not be used to endorse or promote
16 *    products derived from this software without specific prior
17 *    written permission.
18 *
19 * This software is provided "AS IS" without warranty of any kind,
20 * either expressed or implied, including, but not limited to, the
21 * implied warranties of merchantability, title and fitness for a
22 * particular purpose.
23 *
24 *------------------------------------------------------------------
25 *
26 *  $Id$
27 */
28
29#include <bsp.h>
30
31/* define tcp struct pointers */
32struct clock_ram * const tcp_power_up =
33   (struct clock_ram * const)(0x16*2+TCP_BASE_ADDRESS);
34
35struct clock_ram * const tcp_power_down =
36   (struct clock_ram * const)(0x1b*2+TCP_BASE_ADDRESS);
37
38struct clock_counters * const tcp_clock =
39   (struct clock_counters * const)(0x05*2+TCP_BASE_ADDRESS);
40
41struct clock_ram * const tcp_save_ram =
42   (struct clock_ram * const)(0x19*2+TCP_BASE_ADDRESS);
43
44#define X_DELAY 300             /* time-out delay for crystal start */
45#define X1_DELAY 100000
46
47void tcp_delay(int count)
48{
49  int i;
50  /* change latter to use a counter !!! */
51  for (i=0;i<count/4;i++);
52}
53
54void tcp_init()
55{
56  unsigned char low_bat, osc_fail, power_up;
57  unsigned char mon, dom, hrs, min, sec;
58  int i, count;
59
60  /* delay about 60us to ensure TCP is not locked-out */
61  tcp_delay(80);
62
63  /* set normal supply mode and reset test mode bit */
64  *MSR = 0;
65  *PFR = 0;
66
67  /* save oscillator failure condition */
68  *MSR = 0;                     /* set RS and PS to zero */
69  osc_fail = (*PFR & OSF ? 1 : 0);
70  *MSR = PS;
71  *RAM_OSC_FAIL = *RAM_OSC_FAIL || osc_fail;
72
73  *MSR = PS;
74  if (*RAM_OSC_FAIL) {
75    power_up = 1;
76    *MSR = PS;
77    *RAM_POWERUP = power_up;
78    /* clear time counters and power up & down ram */
79    *MSR = 0;
80    tcp_clock->hofs = 0;
81    tcp_clock->sec = 0;
82    tcp_clock->min = 0;
83    tcp_clock->hrs = 0;
84    tcp_clock->dom = 1;
85    tcp_clock->mon = 1;
86    tcp_clock->yr = 0x95;
87    tcp_clock->jd0 = 0x01;
88    tcp_clock->jd1 = 0;
89    tcp_clock->dow = 1;
90    *MSR = PS;
91    tcp_power_up->sec = 0;
92    tcp_power_up->min = 0;
93    tcp_power_up->hrs = 0;
94    tcp_power_up->dom = 0;
95    tcp_power_up->mon = 0;
96    tcp_power_down->sec = 0;
97    tcp_power_down->min = 0;
98    tcp_power_down->hrs = 0;
99    tcp_power_down->dom = 0;
100    tcp_power_down->mon = 0;
101  } else {
102    /* save for power-up test */
103    *MSR = 0;
104    power_up = (*IRR & TMSE ? 0 : 1);
105    *MSR = PS;
106    *RAM_POWERUP = power_up;
107
108    /* update tcp_power_up and tcp_power_down on power up */
109    if (power_up) {
110      *MSR = 0;
111      do {
112        *PFR;
113        sec = tcp_clock->sec;
114        min = tcp_clock->min;
115        hrs = tcp_clock->hrs;
116        dom = tcp_clock->dom;
117        mon = tcp_clock->mon;
118      } while (*PFR & R_1S);
119      *MSR = PS;
120      tcp_power_up->sec = sec;
121      tcp_power_up->min = min;
122      tcp_power_up->hrs = hrs;
123      tcp_power_up->dom = dom;
124      tcp_power_up->mon = ( (((mon>>4)*10)+(mon&0xf))>12 ? 0 : mon );
125      *MSR = 0;                 /* save ram is not running */
126      sec = tcp_save_ram->sec;
127      min = tcp_save_ram->min;
128      hrs = tcp_save_ram->hrs;
129      dom = tcp_save_ram->dom;
130      mon = tcp_save_ram->mon;
131      *MSR = PS;
132      tcp_power_down->sec = sec;
133      tcp_power_down->min = min;
134      tcp_power_down->hrs = hrs;
135      tcp_power_down->dom = dom;
136      tcp_power_down->mon = ( (((mon>>4)*10)+(mon&0xf))>12 ? 0 : mon );
137    }
138  }
139
140  /* load interrupt routing reg. PF must be enabled to test
141     for low battery, but I route it to MFO to avoid any
142     potential problems */
143  *MSR = 0;
144  *IRR = PF_R | TMSE;
145
146  /* initialize the output mode register */
147  *MSR = RS;
148  *OMR = IP | MP | MO;          /* INTR active low and push/pull */
149
150  /* initialize interrupt control reg 0 */
151  *MSR = RS;
152  *ICR0 = 0;                    /* disable all interrupts */
153
154  /* initialize interrupt control reg 1 */
155  *MSR = RS;
156  *ICR1 = PFE;                  /* this also enables the low battery
157                                   detection circuit. */
158
159  /* I had trouble getting the tcp to be completely
160     flexible to supply modes (i.e., automatically
161     selecting single or normal battery backup modes based
162     on inputs at power-up. If single supply mode is
163     selected, the low battery detect is disabled and the
164     low battery detect in normal mode does not seem to
165     detect when no battery is present at all. If normal
166     mode is selected and no battery is present, the
167     crystal will stop, but only if reset after
168     power-up. It would seem that after a power-up reset,
169     with no battery, the chip may automaticlly switch to
170     single supply mode which disables the low battery
171     detection circuit.)  The following software tests
172     works for all permiatations of low batt, reset,
173     power-on reset, battery, no battery, battery on after
174     Vcc,....  *except* for battery switched on for the
175     first time before power up in which case the chip
176     will still be in single suppy mode till restarted (a
177     second call to tcp_init such as when the time is set
178     or a reboot.)  The timer/clock itself should always
179     be completely functional regardless of the supply
180     mode. */
181
182
183  /* initialize the real time mode register */
184  /* note: write mode bits *before* CSS, then set CSS */
185  *MSR = 0;                     /* clear roll-over */
186  *PFR;
187  count=1;
188  for (i=0;i<X_DELAY;i++) {     /* loop till xtal starts */
189    *MSR = RS;
190    *RTMR = (*RTMR & (LY0 | LY1 )) | CSS;
191    *MSR = 0;
192    if (*PFR & R_1MS) 
193      if (!(count--)) break;
194  }
195  if (i>=X_DELAY) {
196    {
197      /* xtal didn't start; try single supply mode */
198      *MSR = 0;                 /* single supply */
199      *PFR = OSF;
200      *MSR = 0;                 /* clear roll-over */
201      *PFR;
202      count=1;
203      for (i=0;i<X1_DELAY;i++) {        /* loop till xtal starts */
204        *MSR = RS;
205        *RTMR = (*RTMR & (LY0 | LY1 )) | CSS;
206        *MSR = 0;
207        if (*PFR & R_1MS)
208          if (!(count--)) break;
209      }
210      if (i>=X1_DELAY) {
211        /* xtal didn't start; fail tcp */
212        *MSR = PS;
213        *RAM_TCP_FAILURE = 1;
214        *MSR = PS;
215        *RAM_SINGLE_SUP=1;
216      } else {
217        *MSR = PS;
218        *RAM_TCP_FAILURE = 0;
219        *MSR = PS;
220        *RAM_SINGLE_SUP=1;
221      }
222    }
223  } else {
224    *MSR = PS;
225    *RAM_TCP_FAILURE = 0;
226    *MSR = PS;
227    *RAM_SINGLE_SUP=0;
228  }
229
230  /* wait for low battery detection circuit to stabalize */
231  tcp_delay(1000);
232
233  /* battery test */
234  *MSR = 0;
235  low_bat = (*IRR & LBF ? 1 : 0 );
236  *MSR = PS;
237  *RAM_LOWBAT = low_bat & !(*RAM_SINGLE_SUP);
238
239  /* reset pending interrupts */
240  *MSR = ( PER | AL | T0 | T1 );
241
242  /* resync the time save ram with the clock */
243  tcp_save_ram->sec = 0;
244  tcp_save_ram->min = 0;
245  tcp_save_ram->hrs = 0;
246  tcp_save_ram->dom = 0;
247  tcp_save_ram->mon = 0;
248} 
Note: See TracBrowser for help on using the repository browser.