[486c329] | 1 | /* |
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| 2 | *------------------------------------------------------------------- |
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| 3 | * |
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| 4 | * DP8570A -- header file for National Semiconducor's DP8570A TCP |
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| 5 | * |
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| 6 | * This file has been created by John S. Gwynne for the efi68k |
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| 7 | * project. |
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| 8 | * |
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| 9 | * Redistribution and use in source and binary forms are permitted |
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| 10 | * provided that the following conditions are met: |
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| 11 | * 1. Redistribution of source code and documentation must retain |
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| 12 | * the above authorship, this list of conditions and the |
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| 13 | * following disclaimer. |
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| 14 | * 2. The name of the author may not be used to endorse or promote |
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| 15 | * products derived from this software without specific prior |
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| 16 | * written permission. |
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| 17 | * |
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| 18 | * This software is provided "AS IS" without warranty of any kind, |
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| 19 | * either expressed or implied, including, but not limited to, the |
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| 20 | * implied warranties of merchantability, title and fitness for a |
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| 21 | * particular purpose. |
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| 22 | * |
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| 23 | *------------------------------------------------------------------ |
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| 24 | * |
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| 25 | * $Id$ |
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| 26 | */ |
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| 27 | |
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| 28 | #ifndef _DP8570A_H_ |
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| 29 | #define _DP8570A_H_ |
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| 30 | |
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| 31 | /* base address is the physical location of register 0 */ |
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| 32 | #define TCP_BASE_ADDRESS 0x0600001 |
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| 33 | |
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| 34 | |
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| 35 | /* definitions of register addresses and associate bits */ |
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| 36 | |
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| 37 | /* ********************************************************* */ |
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| 38 | /* Control Registers */ |
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| 39 | /* ********************************************************* */ |
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| 40 | |
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| 41 | /* REMEMBER: if you are in an interrupt routine, you must |
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| 42 | reset RS and PS of MSR to the value they had on entry |
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| 43 | to the ISR before exiting */ |
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| 44 | |
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| 45 | #define MSR (volatile unsigned char * const)(0x00*2+TCP_BASE_ADDRESS) |
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| 46 | /* Main Status Register */ |
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| 47 | #define INT 0x01 /* Interrupt Status */ |
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| 48 | #define PF 0x02 /* Power Fail Interrupt */ |
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| 49 | #define PER 0x04 /* Period Interrupt */ |
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| 50 | #define AL 0x08 /* Alarm Interrupt */ |
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| 51 | #define T0 0x10 /* Timer 0 Interrupt */ |
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| 52 | #define T1 0x20 /* Timer 1 Interrupt */ |
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| 53 | #define RS 0x40 /* Register Select Bit */ |
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| 54 | #define PS 0x80 /* Page Select Bit */ |
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| 55 | |
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| 56 | #define T0CR (volatile unsigned char * const)(0x01*2+TCP_BASE_ADDRESS) |
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| 57 | /* Timer 0 Control Register */ |
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| 58 | #define T1CR (volatile unsigned char * const)(0x02*2+TCP_BASE_ADDRESS) |
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| 59 | /* Timer 1 Control Register */ |
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| 60 | #define TSS 0x01 /* Timer Start/!Stop */ |
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| 61 | #define M0 0x02 /* Mode Select */ |
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| 62 | #define M1 0x04 /* Mode Select */ |
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| 63 | #define C0 0x08 /* Input Clock Select */ |
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| 64 | #define C1 0x10 /* Input Clock Select */ |
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| 65 | #define C2 0x20 /* Input Clock Select */ |
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| 66 | #define RD 0x40 /* Timer Read */ |
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| 67 | #define CHG 0x80 /* Count Hold/Gate */ |
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| 68 | |
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| 69 | #define PFR (volatile unsigned char * const)(0x03*2+TCP_BASE_ADDRESS) |
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| 70 | /* Periodic Flag Register */ |
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| 71 | #define R_1MIN 0x01 /* Minute Flage */ |
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| 72 | #define R_10S 0x02 /* 10 Second Flag */ |
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| 73 | #define R_1S 0x04 /* Second Flag */ |
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| 74 | #define R_100MS 0x08 /* 100 Millisec Flag */ |
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| 75 | #define R_10MS 0x10 /* 10 Millisec Flag */ |
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| 76 | #define R_1MS 0x20 /* 1 Millisec Flag */ |
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| 77 | #define OSF 0x40 /* Oscillator Failed/Single Supply */ |
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| 78 | #define TMODE 0x80 /* Test Mode Enable */ |
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| 79 | |
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| 80 | #define IRR (volatile unsigned char * const)(0x04*2+TCP_BASE_ADDRESS) |
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| 81 | /* Interrupt Routing Register */ |
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| 82 | #define PF_R 0x01 /* Power Fail Route */ |
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| 83 | #define PR_R 0x02 /* Periodic Route */ |
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| 84 | #define AL_R 0x04 /* Alarm Route */ |
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| 85 | #define T0_R 0x08 /* Timer 0 Route */ |
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| 86 | #define T1_R 0x10 /* Timer 1 Route */ |
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| 87 | #define PFD 0x20 /* PF Delay Enable */ |
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| 88 | #define LBF 0x40 /* Low Battery Flag */ |
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| 89 | #define TMSE 0x80 /* Time Save Enable */ |
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| 90 | |
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| 91 | #define RTMR (volatile unsigned char * const)(0x01*2+TCP_BASE_ADDRESS) |
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| 92 | /* Real Time Mode Register */ |
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| 93 | #define LY0 0x01 /* Leap Year LSB */ |
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| 94 | #define LY1 0x02 /* Leap Year MSB */ |
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| 95 | #define H12 0x04 /* 12/!24 Hour Mode */ |
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| 96 | #define CSS 0x08 /* Clock Start/!Stop */ |
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| 97 | #define IPF 0x10 /* Interrupt PF Operation */ |
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| 98 | #define TPF 0x20 /* Timer PF Operation */ |
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| 99 | #define XT0 0x40 /* Crystal Frequency LSB */ |
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| 100 | #define XT1 0x80 /* Crystal Frequency MSB */ |
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| 101 | |
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| 102 | #define OMR (volatile unsigned char * const)(0x02*2+TCP_BASE_ADDRESS) |
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| 103 | /* Output Mode Register */ |
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| 104 | #define TH 0x01 /* T1 Active Hi/!Low */ |
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| 105 | #define TP 0x02 /* T1 Push Pull/!Open Drain */ |
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| 106 | #define IH 0x04 /* INTR Active Hi/!Low */ |
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| 107 | #define IP 0x08 /* INTR Push Pull/!Open Drain */ |
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| 108 | #define MH 0x10 /* MFO Active Hi/!Low */ |
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| 109 | #define MP 0x20 /* MFO Push Pull/!Open Drain */ |
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| 110 | #define MT 0x40 /* MFO Pin as Timer 0 */ |
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| 111 | #define MO 0x80 /* MFO Pin as Oscillator */ |
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| 112 | |
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| 113 | #define ICR0 (volatile unsigned char * const)(0x03*2+TCP_BASE_ADDRESS) |
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| 114 | /* Interrupt control Register 0 */ |
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| 115 | #define ME 0x01 /* Minutes Enable */ |
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| 116 | #define TSE 0x02 /* 10 Second Enable */ |
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| 117 | #define SE 0x04 /* Seconds Enable */ |
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| 118 | #define HME 0x08 /* 100 Millisec Enable */ |
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| 119 | #define TME 0x10 /* 10 Millisec Enable */ |
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| 120 | #define OME 0x20 /* Millisec Enable */ |
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| 121 | #define T0E 0x40 /* Timer 0 Enable */ |
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| 122 | #define T1E 0x80 /* Timer 1 Enable */ |
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| 123 | |
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| 124 | #define ICR1 (volatile unsigned char * const)(0x04*2+TCP_BASE_ADDRESS) |
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| 125 | /* Interrupt control Register 1 */ |
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| 126 | #define SCE 0x01 /* Second Compare Enable */ |
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| 127 | #define MNE 0x02 /* Minute Compare Enable */ |
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| 128 | #define HRE 0x04 /* Hour Compare Enable */ |
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| 129 | #define DOME 0x08 /* Day of Month Compare Enable */ |
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| 130 | #define MOE 0x10 /* Month Compare Enable */ |
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| 131 | #define DOWE 0x20 /* Day of Week Compare Enable */ |
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| 132 | #define ALE 0x40 /* Alarm Interrupt Enable */ |
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| 133 | #define PFE 0x80 /* Power Fail Interrupt Enable */ |
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| 134 | |
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| 135 | |
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| 136 | |
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| 137 | /* ********************************************************* */ |
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| 138 | /* Counters: Clock and Calendar (data is stored in BCD) */ |
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| 139 | /* ********************************************************* */ |
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| 140 | #define HOFS (volatile unsigned char * const)(0x05*2+TCP_BASE_ADDRESS) |
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| 141 | /* Hundredth of Seconds */ |
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| 142 | #define SEC (volatile unsigned char * const)(0x06*2+TCP_BASE_ADDRESS) |
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| 143 | /* Seconds */ |
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| 144 | #define MIN (volatile unsigned char * const)(0x07*2+TCP_BASE_ADDRESS) |
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| 145 | /* Minutes */ |
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| 146 | #define HRS (volatile unsigned char * const)(0x08*2+TCP_BASE_ADDRESS) |
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| 147 | /* Hours */ |
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| 148 | #define DOM (volatile unsigned char * const)(0x09*2+TCP_BASE_ADDRESS) |
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| 149 | /* Day of Month */ |
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| 150 | #define MON (volatile unsigned char * const)(0x0a*2+TCP_BASE_ADDRESS) |
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| 151 | /* Month */ |
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| 152 | #define YR (volatile unsigned char * const)(0x0b*2+TCP_BASE_ADDRESS) |
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| 153 | /* Year */ |
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| 154 | #define JD_LSB (volatile unsigned char * const)(0x0c*2+TCP_BASE_ADDRESS) |
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| 155 | /* Julian Date (LSB) */ |
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| 156 | #define JD_MSM (volatile unsigned char * const)(0x0d*2+TCP_BASE_ADDRESS) |
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| 157 | /* Julian Date (MSB) */ |
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| 158 | #define DOW (volatile unsigned char * const)(0x0e*2+TCP_BASE_ADDRESS) |
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| 159 | /* Day of week */ |
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| 160 | |
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| 161 | |
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| 162 | /* ********************************************************* */ |
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| 163 | /* Timer Data Registers */ |
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| 164 | /* ********************************************************* */ |
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| 165 | #define T0_LSB (volatile unsigned char * const)(0x0f*2+TCP_BASE_ADDRESS) |
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| 166 | /* Timer 0 LSB */ |
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| 167 | #define T0_MSB (volatile unsigned char * const)(0x10*2+TCP_BASE_ADDRESS) |
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| 168 | /* Timer 0 MSB */ |
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| 169 | #define T1_LSB (volatile unsigned char * const)(0x11*2+TCP_BASE_ADDRESS) |
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| 170 | /* Timer 1 LSB */ |
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| 171 | #define T1_MSB (volatile unsigned char * const)(0x12*2+TCP_BASE_ADDRESS) |
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| 172 | /* Timer 1 MSB */ |
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| 173 | |
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| 174 | |
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| 175 | /* ********************************************************* */ |
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| 176 | /* Timer Compare RAM */ |
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| 177 | /* ********************************************************* */ |
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| 178 | #define TC_SEC (volatile unsigned char * const)(0x13*2+TCP_BASE_ADDRESS) |
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| 179 | /* Seconds Compare RAM */ |
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| 180 | #define TC_MIN (volatile unsigned char * const)(0x14*2+TCP_BASE_ADDRESS) |
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| 181 | /* Minutes Compare RAM */ |
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| 182 | #define TC_HRS (volatile unsigned char * const)(0x15*2+TCP_BASE_ADDRESS) |
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| 183 | /* Hours Compare RAM */ |
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| 184 | #define TC_DOM (volatile unsigned char * const)(0x16*2+TCP_BASE_ADDRESS) |
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| 185 | /* Day of Month Compare RAM */ |
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| 186 | #define TC_MON (volatile unsigned char * const)(0x17*2+TCP_BASE_ADDRESS) |
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| 187 | /* Month Compare RAM */ |
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| 188 | #define TC_DOW (volatile unsigned char * const)(0x18*2+TCP_BASE_ADDRESS) |
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| 189 | /* Day of Week Compare RAM */ |
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| 190 | |
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| 191 | |
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| 192 | /* ********************************************************* */ |
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| 193 | /* Time Save RAM */ |
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| 194 | /* ********************************************************* */ |
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| 195 | #define S_SEC (volatile unsigned char * const)(0x19*2+TCP_BASE_ADDRESS) |
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| 196 | /* Seconds Save RAM */ |
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| 197 | #define S_MIN (volatile unsigned char * const)(0x1a*2+TCP_BASE_ADDRESS) |
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| 198 | /* Minutes Save RAM */ |
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| 199 | #define S_HRS (volatile unsigned char * const)(0x1b*2+TCP_BASE_ADDRESS) |
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| 200 | /* Hours Save RAM */ |
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| 201 | #define S_DOM (volatile unsigned char * const)(0x1c*2+TCP_BASE_ADDRESS) |
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| 202 | /* Day of Month Save RAM */ |
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| 203 | #define S_MON (volatile unsigned char * const)(0x1d*2+TCP_BASE_ADDRESS) |
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| 204 | /* Month Save RAM */ |
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| 205 | |
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| 206 | |
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| 207 | /* ********************************************************* */ |
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| 208 | /* Miscellaneous Registers */ |
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| 209 | /* ********************************************************* */ |
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| 210 | /* rem: 0x1e is general purpose RAM */ |
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| 211 | #define TMR (volatile unsigned char * const)(0x1F*2+TCP_BASE_ADDRESS) |
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| 212 | /* RAM/Test Mode Register */ |
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| 213 | |
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| 214 | |
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| 215 | |
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| 216 | /* ********************************************************* */ |
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| 217 | /* RAM allocation */ |
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| 218 | /* ********************************************************* */ |
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| 219 | #define RAM_OSC_FAIL (volatile unsigned char * const)(0x01*2+TCP_BASE_ADDRESS) |
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| 220 | /* 1: osc. failed time lost */ |
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| 221 | #define RAM_POWERUP (volatile unsigned char * const)(0x02*2+TCP_BASE_ADDRESS) |
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| 222 | /* 1: power was removed and the applied |
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| 223 | before last TCP init */ |
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| 224 | #define RAM_LOWBAT (volatile unsigned char * const)(0x03*2+TCP_BASE_ADDRESS) |
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| 225 | /* 1: battery voltage is low (2.2V) */ |
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| 226 | /* not valid in single supply mode */ |
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| 227 | #define RAM_SINGLE_SUP (volatile unsigned char * const)(0x04*2+TCP_BASE_ADDRESS) |
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| 228 | /* 1: single supply mode */ |
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| 229 | /* note: single supply mode will be |
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| 230 | selected when no backup battery is |
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| 231 | present and/or the first time the |
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| 232 | system is booted after the loss of |
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| 233 | backup battery voltage. */ |
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| 234 | #define RAM_TCP_FAILURE (volatile unsigned char * const)(0x05*2+TCP_BASE_ADDRESS) |
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| 235 | /* 1: TCP failed to start oscillating */ |
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| 236 | |
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| 237 | |
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| 238 | /* ********************************************************* */ |
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| 239 | /* TCP data structures */ |
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| 240 | /* ********************************************************* */ |
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| 241 | |
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| 242 | struct clock_counters { |
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| 243 | unsigned char hofs; |
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| 244 | unsigned char d0; /* the dx's are place holders since */ |
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| 245 | unsigned char sec; /* the TCP is addressable only on */ |
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| 246 | unsigned char d1; /* odd addresses. */ |
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| 247 | unsigned char min; |
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| 248 | unsigned char d2; |
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| 249 | unsigned char hrs; |
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| 250 | unsigned char d3; |
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| 251 | unsigned char dom; |
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| 252 | unsigned char d4; |
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| 253 | unsigned char mon; |
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| 254 | unsigned char d5; |
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| 255 | unsigned char yr; |
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| 256 | unsigned char d6; |
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| 257 | unsigned char jd0; |
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| 258 | unsigned char d7; |
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| 259 | unsigned char jd1; |
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| 260 | unsigned char d8; |
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| 261 | unsigned char dow; |
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| 262 | }; |
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| 263 | |
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| 264 | extern struct clock_ram * const tcp_power_up; |
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| 265 | |
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| 266 | struct clock_ram { |
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| 267 | unsigned char sec; |
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| 268 | unsigned char d0; /* the dx's are place holders since */ |
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| 269 | unsigned char min; /* the TCP is addressable only on */ |
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| 270 | unsigned char d1; /* odd addresses. */ |
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| 271 | unsigned char hrs; |
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| 272 | unsigned char d2; |
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| 273 | unsigned char dom; |
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| 274 | unsigned char d3; |
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| 275 | unsigned char mon; |
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| 276 | }; |
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| 277 | |
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| 278 | extern struct clock_ram * const tcp_power_up; |
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| 279 | extern struct clock_ram * const tcp_power_down; |
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| 280 | extern struct clock_counters * const tcp_clock; |
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| 281 | extern struct clock_ram * const tcp_save_ram; |
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| 282 | |
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| 283 | void tcp_init(void); |
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| 284 | |
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| 285 | #endif /* _DP8570A_H_ */ |
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