source: rtems/c/src/lib/libbsp/m68k/efi68k/include/16550.h @ a858910

4.104.114.84.95
Last change on this file since a858910 was 18647b7, checked in by Joel Sherrill <joel.sherrill@…>, on 04/25/97 at 16:58:10

updated to reflect new license per John Gwynne's permission.
  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*
2 *-------------------------------------------------------------------
3 *
4 *   16550 -- header file for National Semiconducor's 16550 UART
5 *
6 * This file has been created by John S. Gwynne for the efi68k
7 * project.
8 *
9 *  The license and distribution terms for this file may in
10 *  the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *------------------------------------------------------------------
14 *
15 *  $Id$
16 */
17
18#ifndef _16550_H_
19#define _16550_H_
20
21/* base address is the physical location of register 0 */
22#define UART_BASE_ADDRESS 0x0400001
23
24/* definitions of register addresses and associate bits */
25
26#define RBR (volatile unsigned char * const)(0*2+UART_BASE_ADDRESS)     
27                                /* Receiver Buffer Register (w/DLAB=0)*/
28                                /*    8-bit data */
29
30#define THR (volatile unsigned char * const)(0*2+UART_BASE_ADDRESS)     
31                                /* Transmitter Holding Register (w/DLAB=0) */
32                                /*    8-bit data */
33
34#define DLL (volatile unsigned char * const)(0*2+UART_BASE_ADDRESS)
35                                /* Divisor Latch (LS) (w/DLAB=1) */
36                                /*    LSB of Divisor */
37
38#define DLM (volatile unsigned char * const)(1*2+UART_BASE_ADDRESS)
39                                /* Divisor Latch (MS) (w/DLAB=1) */
40                                /*    MSB of Divisor */
41
42#define IER (volatile unsigned char * const)(1*2+UART_BASE_ADDRESS)
43                                /* Interrupt Enable Register (w/DLAB=0) */
44#define    ERBFI 0x01           /*    Enable Recv Data Available Interrupt */
45#define    ETBEI 0x02           /*    Enable Trans Holding Reg Empty Inter */
46#define    ELSI  0x04           /*    Enable Recv Line Status Interrupt */
47#define    EDSSI 0x08           /*    Enable Modem Status Interrupt */
48
49#define IIR (volatile unsigned char * const)(2*2+UART_BASE_ADDRESS)
50                                /* Interrupt Ident Register (read only) */
51#define    NIP   0x01           /*    No Interrupt Pending */
52#define    IID_MASK 0x0e        /*    Interrupt ID mask */
53#define    FE_MASK 0xc0         /*    FIFO's Enabled */
54
55#define FCR (volatile unsigned char * const)(2*2+UART_BASE_ADDRESS)
56                                /* FIFO Control Register (write only) */
57#define    FIFO_E 0x01          /*    FIFO Enable */
58#define    RFR   0x02           /*    RCVR FIFO Reset */
59#define    XFR   0x04           /*    XMIT FIFO Reset */
60#define    DMAMS 0x08           /*    DMA Mode Select */
61#define    RCVRTG_MASK 0xC0     /*    RCVR Triger MSBit/LSBit */
62
63#define LCR (volatile unsigned char * const)(3*2+UART_BASE_ADDRESS)
64                                /* Line Control Register */
65#define    WLS_MASK 0x03        /*    Word Legth Select Mask */
66#define       WL_5 0x00         /*       5 bits */
67#define       WL_6 0x01         /*       6 bits */
68#define       WL_7 0x02         /*       7 bits */
69#define       WL_8 0x03         /*       8 bits */
70#define    NSB   0x04           /*    Number of Stop Bits (set is 2/1.5) */
71#define    PEN   0x08           /*    Parity Enable */
72#define    EPS   0x10           /*    Even Parity Select */
73#define    STP   0x20           /*    Stick Parity */
74#define    SETBK 0x40           /*    Set Break */
75#define    DLAB  0x80           /*    Divisor Latch Access Bit */
76
77#define MCR (volatile unsigned char * const)(4*2+UART_BASE_ADDRESS)
78                                /* Modem Control Register */
79#define    DTR   0x01           /*    Data Terminal Ready */
80#define    RTS   0x02           /*    Request to Send */
81#define    OUT1  0x04           /*    Out 1 */
82#define    OUT2  0x08           /*    Out 2 */
83#define    LOOP  0x10           /*    Loop */
84
85#define LSR (volatile unsigned char * const)(5*2+UART_BASE_ADDRESS)
86                                /* Line Status Register */
87#define    DR    0x01           /*    Data Ready */
88#define    OE    0x02           /*    Overrun error */
89#define    PE    0x04           /*    Parity error */
90#define    FE    0x08           /*    Framing error */
91#define    BI    0x10           /*    Break Interrupt */
92#define    THRE  0x20           /*    Transmitter Holding Register */
93#define    TEMT  0x40           /*    Transmitter Empty */
94#define    RCVFIE 0x80          /*    Recv FIFO Error */
95
96#define MDSR (volatile unsigned char * const)(6*2+UART_BASE_ADDRESS)
97                                /* Modem Status Register */
98#define    DCTS  0x01           /*    Delta Clear to Send */
99#define    DDSR  0x02           /*    Delta Data Set Ready */
100#define    TERI  0x04           /*    Trailing Edge Ring Indicator */
101#define    DDCD  0x08           /*    Delta Data Carrier Detect */
102#define    CTS   0x10           /*    Clear to Send */
103#define    DSR   0x20           /*    Data Set Ready */
104#define    RI    0x40           /*    Ring Indicator */
105#define    DCD   0x80           /*    Data Carrier Detect */
106
107#define SCR (volatile unsigned char * const)(7*2+UART_BASE_ADDRESS)
108                                /* Scratch Register */
109                                /*    8-bit register */
110#endif
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