1 | /* |
---|
2 | *------------------------------------------------------------------- |
---|
3 | * |
---|
4 | * 16550 -- header file for National Semiconducor's 16550 UART |
---|
5 | * |
---|
6 | * This file has been created by John S. Gwynne for the efi68k |
---|
7 | * project. |
---|
8 | * |
---|
9 | * Redistribution and use in source and binary forms are permitted |
---|
10 | * provided that the following conditions are met: |
---|
11 | * 1. Redistribution of source code and documentation must retain |
---|
12 | * the above authorship, this list of conditions and the |
---|
13 | * following disclaimer. |
---|
14 | * 2. The name of the author may not be used to endorse or promote |
---|
15 | * products derived from this software without specific prior |
---|
16 | * written permission. |
---|
17 | * |
---|
18 | * This software is provided "AS IS" without warranty of any kind, |
---|
19 | * either expressed or implied, including, but not limited to, the |
---|
20 | * implied warranties of merchantability, title and fitness for a |
---|
21 | * particular purpose. |
---|
22 | * |
---|
23 | *------------------------------------------------------------------ |
---|
24 | * |
---|
25 | * $Id$ |
---|
26 | */ |
---|
27 | |
---|
28 | #ifndef _16550_H_ |
---|
29 | #define _16550_H_ |
---|
30 | |
---|
31 | /* base address is the physical location of register 0 */ |
---|
32 | #define UART_BASE_ADDRESS 0x0400001 |
---|
33 | |
---|
34 | /* definitions of register addresses and associate bits */ |
---|
35 | |
---|
36 | #define RBR (volatile unsigned char * const)(0*2+UART_BASE_ADDRESS) |
---|
37 | /* Receiver Buffer Register (w/DLAB=0)*/ |
---|
38 | /* 8-bit data */ |
---|
39 | |
---|
40 | #define THR (volatile unsigned char * const)(0*2+UART_BASE_ADDRESS) |
---|
41 | /* Transmitter Holding Register (w/DLAB=0) */ |
---|
42 | /* 8-bit data */ |
---|
43 | |
---|
44 | #define DLL (volatile unsigned char * const)(0*2+UART_BASE_ADDRESS) |
---|
45 | /* Divisor Latch (LS) (w/DLAB=1) */ |
---|
46 | /* LSB of Divisor */ |
---|
47 | |
---|
48 | #define DLM (volatile unsigned char * const)(1*2+UART_BASE_ADDRESS) |
---|
49 | /* Divisor Latch (MS) (w/DLAB=1) */ |
---|
50 | /* MSB of Divisor */ |
---|
51 | |
---|
52 | #define IER (volatile unsigned char * const)(1*2+UART_BASE_ADDRESS) |
---|
53 | /* Interrupt Enable Register (w/DLAB=0) */ |
---|
54 | #define ERBFI 0x01 /* Enable Recv Data Available Interrupt */ |
---|
55 | #define ETBEI 0x02 /* Enable Trans Holding Reg Empty Inter */ |
---|
56 | #define ELSI 0x04 /* Enable Recv Line Status Interrupt */ |
---|
57 | #define EDSSI 0x08 /* Enable Modem Status Interrupt */ |
---|
58 | |
---|
59 | #define IIR (volatile unsigned char * const)(2*2+UART_BASE_ADDRESS) |
---|
60 | /* Interrupt Ident Register (read only) */ |
---|
61 | #define NIP 0x01 /* No Interrupt Pending */ |
---|
62 | #define IID_MASK 0x0e /* Interrupt ID mask */ |
---|
63 | #define FE_MASK 0xc0 /* FIFO's Enabled */ |
---|
64 | |
---|
65 | #define FCR (volatile unsigned char * const)(2*2+UART_BASE_ADDRESS) |
---|
66 | /* FIFO Control Register (write only) */ |
---|
67 | #define FIFO_E 0x01 /* FIFO Enable */ |
---|
68 | #define RFR 0x02 /* RCVR FIFO Reset */ |
---|
69 | #define XFR 0x04 /* XMIT FIFO Reset */ |
---|
70 | #define DMAMS 0x08 /* DMA Mode Select */ |
---|
71 | #define RCVRTG_MASK 0xC0 /* RCVR Triger MSBit/LSBit */ |
---|
72 | |
---|
73 | #define LCR (volatile unsigned char * const)(3*2+UART_BASE_ADDRESS) |
---|
74 | /* Line Control Register */ |
---|
75 | #define WLS_MASK 0x03 /* Word Legth Select Mask */ |
---|
76 | #define WL_5 0x00 /* 5 bits */ |
---|
77 | #define WL_6 0x01 /* 6 bits */ |
---|
78 | #define WL_7 0x02 /* 7 bits */ |
---|
79 | #define WL_8 0x03 /* 8 bits */ |
---|
80 | #define NSB 0x04 /* Number of Stop Bits (set is 2/1.5) */ |
---|
81 | #define PEN 0x08 /* Parity Enable */ |
---|
82 | #define EPS 0x10 /* Even Parity Select */ |
---|
83 | #define STP 0x20 /* Stick Parity */ |
---|
84 | #define SETBK 0x40 /* Set Break */ |
---|
85 | #define DLAB 0x80 /* Divisor Latch Access Bit */ |
---|
86 | |
---|
87 | #define MCR (volatile unsigned char * const)(4*2+UART_BASE_ADDRESS) |
---|
88 | /* Modem Control Register */ |
---|
89 | #define DTR 0x01 /* Data Terminal Ready */ |
---|
90 | #define RTS 0x02 /* Request to Send */ |
---|
91 | #define OUT1 0x04 /* Out 1 */ |
---|
92 | #define OUT2 0x08 /* Out 2 */ |
---|
93 | #define LOOP 0x10 /* Loop */ |
---|
94 | |
---|
95 | #define LSR (volatile unsigned char * const)(5*2+UART_BASE_ADDRESS) |
---|
96 | /* Line Status Register */ |
---|
97 | #define DR 0x01 /* Data Ready */ |
---|
98 | #define OE 0x02 /* Overrun error */ |
---|
99 | #define PE 0x04 /* Parity error */ |
---|
100 | #define FE 0x08 /* Framing error */ |
---|
101 | #define BI 0x10 /* Break Interrupt */ |
---|
102 | #define THRE 0x20 /* Transmitter Holding Register */ |
---|
103 | #define TEMT 0x40 /* Transmitter Empty */ |
---|
104 | #define RCVFIE 0x80 /* Recv FIFO Error */ |
---|
105 | |
---|
106 | #define MDSR (volatile unsigned char * const)(6*2+UART_BASE_ADDRESS) |
---|
107 | /* Modem Status Register */ |
---|
108 | #define DCTS 0x01 /* Delta Clear to Send */ |
---|
109 | #define DDSR 0x02 /* Delta Data Set Ready */ |
---|
110 | #define TERI 0x04 /* Trailing Edge Ring Indicator */ |
---|
111 | #define DDCD 0x08 /* Delta Data Carrier Detect */ |
---|
112 | #define CTS 0x10 /* Clear to Send */ |
---|
113 | #define DSR 0x20 /* Data Set Ready */ |
---|
114 | #define RI 0x40 /* Ring Indicator */ |
---|
115 | #define DCD 0x80 /* Data Carrier Detect */ |
---|
116 | |
---|
117 | #define SCR (volatile unsigned char * const)(7*2+UART_BASE_ADDRESS) |
---|
118 | /* Scratch Register */ |
---|
119 | /* 8-bit register */ |
---|
120 | #endif |
---|