source: rtems/c/src/lib/libbsp/m68k/efi332/start332/start332.c @ e2a2ec60

4.104.114.84.95
Last change on this file since e2a2ec60 was e2a2ec60, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 21, 1998 at 3:37:18 PM

Switch to using a shared main() for all of the embedded BSPs
based on the GNU tools. This usually involved correcting the
type of bsp_start(), bsp_cleanup(), adjusting the start code to
call the right start routine (the shared boot_card()), and then
removing code from bsp_start() which was performed in the new
boot_card()/main() path.

  • Property mode set to 100644
File size: 5.8 KB
Line 
1/*
2 *  $Id
3 */
4
5#include <efi332.h>
6#include <sim.h>
7#define __START_C__
8#include "bsp.h"
9
10m68k_isr_entry M68Kvec[256];
11m68k_isr_entry vectors[256];
12char * const __argv[]= {"main", ""};
13char * const __env[]= {""};
14
15/*
16 *  This prototype really should have the noreturn attribute but
17 *  that causes a warning since it appears that the routine does
18 *  return.
19 *
20 *   void dumby_start ()  __attribute__ ((noreturn));
21 */
22
23void dumby_start ();
24void  dumby_start() {
25
26  /* We need to by-pass the link instruction since the RAM chip-
27     select pins are not yet configured. */
28  asm volatile ( ".global start ;
29                  start:");
30
31  /* disable interrupts, load stack pointer */
32  asm volatile ( "oriw  #0x0700, %sr;
33                  moveal #M68Kvec, %a0;
34                  movec %a0, %vbr;
35                  movel  #_end, %d0;
36                  addl   " STACK_SIZE ",%d0;
37                  movel  %d0,%sp;
38                  link %a6, #0"
39                  );
40
41  /* include in ram_init.S */
42  /*
43   * Initalize the SIM module.
44   * The stack pointer is not usable until the RAM chip select lines
45   * are configured. The following code must remain inline.
46   */
47
48  /* Module Configuration Register */
49  /*    see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
50  *SIMCR = (unsigned short int) 
51    (FRZSW | FRZBM | SAM(0,8,SHEN) | (MM*SIM_MM) | SAM(SIM_IARB,0,IARB));
52
53  /* Synthesizer Control Register */
54  /*    see section(s) 4.8 */
55  /* end include in ram_init.S */
56  *SYNCR = (unsigned short int)
57    ( SAM(EFI_W,15,W) | SAM(0x0,14,X) | SAM(EFI_Y,8,Y) | STSIM );
58  while (! (*SYNCR & SLOCK));   /* protect from clock overshoot */
59  /* include in ram_init.S */
60  *SYNCR = (unsigned short int)
61    ( SAM(EFI_W,15,W) | SAM(EFI_X,14,X) | SAM(EFI_Y,8,Y) | STSIM );
62
63  /* System Protection Control Register */
64  /*    !!! can only write to once after reset !!! */
65  /*    see section 3.8.4 of the SIM Reference Manual */
66  *SYPCR = (unsigned char)( SAM(0x3,4,SWT) | HME | BME );
67
68  /* Periodic Interrupr Control Register */
69  /*    see section 3.8.2 of the SIM Reference Manual */
70  *PICR = (unsigned short int)
71    ( SAM(0,8,PIRQL) | SAM(EFI_PIV,0,PIV) );
72  /*     ^^^ zero disables interrupt, don't enable here or ram_init will
73         be wrong. It's enabled below. */
74
75  /* Periodic Interrupt Timer Register */
76  /*    see section 3.8.3 of the SIM Reference Manual */
77  *PITR = (unsigned short int)( SAM(0x09,0,PITM) );
78  /*    1.098mS interrupt */
79
80  /* Port C Data */
81  /*    load values before enabled */
82  *PORTC = (unsigned char) 0x0;
83
84  /* Chip-Select Base Address Register */
85  /*    see section 7 of the SIM Reference Manual */
86  *CSBARBT = (unsigned short int)
87    (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
88  *CSBAR0 = (unsigned short int)
89    (((0x000000 >> 8)&0xfff8) | BS_1M );   /* 1M bytes located at 0x0000 */
90  *CSBAR1 = (unsigned short int)
91    (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
92  *CSBAR2 = (unsigned short int)
93    (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0x80000 */
94  *CSBAR3 = (unsigned short int)         
95    (0xfff8 | BS_64K);                   /* AVEC interrupts */
96  *CSBAR10 = (unsigned short int)
97    (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
98
99  /* Chip-Select Options Registers */
100  /*    see section 7 of the SIM Reference Manual */
101  *CSORBT = (unsigned short int)
102    ( BothBytes | ReadWrite | SyncAS | WaitStates_13 | UserSupSpace );
103  *CSOR0 = (unsigned short int)
104    ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
105  *CSOR1 = (unsigned short int)
106    ( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
107  *CSOR2 = (unsigned short int)
108    ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
109  *CSOR3 = (unsigned short int)
110    ( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC );
111  *CSOR10 = (unsigned short int)
112    ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
113
114  /* Chip Select Pin Assignment Register 0 */
115  /*    see section 7 of the SIM Reference Manual */
116  *CSPAR0 = (unsigned short int)( 
117     SAM(DisOut,CS_5,0x3000) |  /* PC2 */
118     SAM(DisOut,CS_4,0x0c00) |  /* PC1 */
119     SAM(DisOut,CS_3,0x0300) |  /* AVEC (internally) */
120     SAM(CS16bit,CS_2,0x00c0)|  /* RAM UDS */
121     SAM(CS16bit,CS_1,0x0030)|  /* RAM LDS */
122     SAM(CS16bit,CS_0,0x000c)|  /* W/!R */
123     SAM(CS16bit,CSBOOT,0x0003) /* ROM DS */
124     );
125
126  /* Chip Select Pin Assignment Register 1 */
127  /*    see section 7 of the SIM Reference Manual */
128  *CSPAR1 = (unsigned short int)( 
129     SAM(CS16bit,CS_10,0x300)|  /* ECLK */
130     SAM(DisOut,CS_9,0x0c0) |   /* PC6 */
131     SAM(DisOut,CS_8,0x030) |   /* PC5 */
132     SAM(DisOut,CS_7,0x00c) |   /* PC4 */
133     SAM(DisOut,CS_6,0x003)     /* PC3 */
134     );
135
136  /* Port E and F Data Register */
137  /*    see section 9 of the SIM Reference Manual */
138  *PORTE0 = (unsigned char) 0;
139  *PORTF0 = (unsigned char) 0;
140
141  /* Port E and F Data Direction Register */
142  /*    see section 9 of the SIM Reference Manual */
143  *DDRE = (unsigned char) 0xff;
144  *DDRF = (unsigned char) 0xfd;
145 
146  /* Port E and F Pin Assignment Register */
147  /*    see section 9 of the SIM Reference Manual */
148  *PEPAR = (unsigned char) 0;
149  *PFPAR = (unsigned char) 0;
150
151  /* end of SIM initalization code */
152  /* end include in ram_init.S */
153
154
155
156  /*
157   * Initialize RAM by copying the .data section out of ROM (if
158   * needed) and "zero-ing" the .bss section.
159   */
160  {
161    register char *src = _endtext;
162    register char *dst = _sdata;
163
164    if (_copy_data_from_rom)
165      /* ROM has data at end of text; copy it. */
166      while (dst < _edata)
167        *dst++ = *src++;
168   
169    /* Zero bss */
170    for (dst = __bss_start; dst< _end; dst++)
171      *dst = 0;
172  }
173
174  /*
175   * Initalize the board.
176   */
177  Spurious_Initialize();
178  console_init();
179
180  /*
181   * Execute main with arguments argv and environment env
182   */
183  /* main(1, __argv, __env); */
184
185  boot_card();
186
187  reboot();
188}
189
190void reboot() {asm("trap #15");}
191
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