source: rtems/c/src/lib/libbsp/m68k/efi332/start332/start332.c @ 6f9c75c3

4.104.114.84.95
Last change on this file since 6f9c75c3 was 6f9c75c3, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 16, 1998 at 4:56:48 PM

Ralf Corsepius reported a number of missing CVS Id's:

RTEMS is under CVS control and has been since rtems 3.1.16 which was
around May 1995. So I just to add the $Id$. If you notice other files
with missing $Id$'s let me know. I try to keep w\up with it.

Now that you have asked -- I'll attach a list of files lacking an RCS-Id to
this mail. This list has been generated by a little sh-script I'll also
enclose.

  • Property mode set to 100644
File size: 5.9 KB
Line 
1/*
2 *  $Id
3 */
4
5#include <efi332.h>
6#include <sim.h>
7#define __START_C__
8#include "bsp.h"
9
10m68k_isr_entry M68Kvec[256];
11m68k_isr_entry vectors[256];
12char * const __argv[]= {"main", ""};
13char * const __env[]= {""};
14
15int main(const int argc, char * const argv[], char * const env[]);
16
17/*
18 *  This prototype really should have the noreturn attribute but
19 *  that causes a warning since it appears that the routine does
20 *  return.
21 *
22 *   void dumby_start ()  __attribute__ ((noreturn));
23 */
24
25void dumby_start ();
26void  dumby_start() {
27
28  /* We need to by-pass the link instruction since the RAM chip-
29     select pins are not yet configured. */
30  asm volatile ( ".global start ;
31                  start:");
32
33  /* disable interrupts, load stack pointer */
34  asm volatile ( "oriw  #0x0700, %sr;
35                  moveal #M68Kvec, %a0;
36                  movec %a0, %vbr;
37                  movel  #_end, %d0;
38                  addl   " STACK_SIZE ",%d0;
39                  movel  %d0,%sp;
40                  link %a6, #0"
41                  );
42
43  /* include in ram_init.S */
44  /*
45   * Initalize the SIM module.
46   * The stack pointer is not usable until the RAM chip select lines
47   * are configured. The following code must remain inline.
48   */
49
50  /* Module Configuration Register */
51  /*    see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
52  *SIMCR = (unsigned short int) 
53    (FRZSW | FRZBM | SAM(0,8,SHEN) | (MM*SIM_MM) | SAM(SIM_IARB,0,IARB));
54
55  /* Synthesizer Control Register */
56  /*    see section(s) 4.8 */
57  /* end include in ram_init.S */
58  *SYNCR = (unsigned short int)
59    ( SAM(EFI_W,15,W) | SAM(0x0,14,X) | SAM(EFI_Y,8,Y) | STSIM );
60  while (! (*SYNCR & SLOCK));   /* protect from clock overshoot */
61  /* include in ram_init.S */
62  *SYNCR = (unsigned short int)
63    ( SAM(EFI_W,15,W) | SAM(EFI_X,14,X) | SAM(EFI_Y,8,Y) | STSIM );
64
65  /* System Protection Control Register */
66  /*    !!! can only write to once after reset !!! */
67  /*    see section 3.8.4 of the SIM Reference Manual */
68  *SYPCR = (unsigned char)( SAM(0x3,4,SWT) | HME | BME );
69
70  /* Periodic Interrupr Control Register */
71  /*    see section 3.8.2 of the SIM Reference Manual */
72  *PICR = (unsigned short int)
73    ( SAM(0,8,PIRQL) | SAM(EFI_PIV,0,PIV) );
74  /*     ^^^ zero disables interrupt, don't enable here or ram_init will
75         be wrong. It's enabled below. */
76
77  /* Periodic Interrupt Timer Register */
78  /*    see section 3.8.3 of the SIM Reference Manual */
79  *PITR = (unsigned short int)( SAM(0x09,0,PITM) );
80  /*    1.098mS interrupt */
81
82  /* Port C Data */
83  /*    load values before enabled */
84  *PORTC = (unsigned char) 0x0;
85
86  /* Chip-Select Base Address Register */
87  /*    see section 7 of the SIM Reference Manual */
88  *CSBARBT = (unsigned short int)
89    (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
90  *CSBAR0 = (unsigned short int)
91    (((0x000000 >> 8)&0xfff8) | BS_1M );   /* 1M bytes located at 0x0000 */
92  *CSBAR1 = (unsigned short int)
93    (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
94  *CSBAR2 = (unsigned short int)
95    (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0x80000 */
96  *CSBAR3 = (unsigned short int)         
97    (0xfff8 | BS_64K);                   /* AVEC interrupts */
98  *CSBAR10 = (unsigned short int)
99    (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
100
101  /* Chip-Select Options Registers */
102  /*    see section 7 of the SIM Reference Manual */
103  *CSORBT = (unsigned short int)
104    ( BothBytes | ReadWrite | SyncAS | WaitStates_13 | UserSupSpace );
105  *CSOR0 = (unsigned short int)
106    ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
107  *CSOR1 = (unsigned short int)
108    ( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
109  *CSOR2 = (unsigned short int)
110    ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
111  *CSOR3 = (unsigned short int)
112    ( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC );
113  *CSOR10 = (unsigned short int)
114    ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
115
116  /* Chip Select Pin Assignment Register 0 */
117  /*    see section 7 of the SIM Reference Manual */
118  *CSPAR0 = (unsigned short int)( 
119     SAM(DisOut,CS_5,0x3000) |  /* PC2 */
120     SAM(DisOut,CS_4,0x0c00) |  /* PC1 */
121     SAM(DisOut,CS_3,0x0300) |  /* AVEC (internally) */
122     SAM(CS16bit,CS_2,0x00c0)|  /* RAM UDS */
123     SAM(CS16bit,CS_1,0x0030)|  /* RAM LDS */
124     SAM(CS16bit,CS_0,0x000c)|  /* W/!R */
125     SAM(CS16bit,CSBOOT,0x0003) /* ROM DS */
126     );
127
128  /* Chip Select Pin Assignment Register 1 */
129  /*    see section 7 of the SIM Reference Manual */
130  *CSPAR1 = (unsigned short int)( 
131     SAM(CS16bit,CS_10,0x300)|  /* ECLK */
132     SAM(DisOut,CS_9,0x0c0) |   /* PC6 */
133     SAM(DisOut,CS_8,0x030) |   /* PC5 */
134     SAM(DisOut,CS_7,0x00c) |   /* PC4 */
135     SAM(DisOut,CS_6,0x003)     /* PC3 */
136     );
137
138  /* Port E and F Data Register */
139  /*    see section 9 of the SIM Reference Manual */
140  *PORTE0 = (unsigned char) 0;
141  *PORTF0 = (unsigned char) 0;
142
143  /* Port E and F Data Direction Register */
144  /*    see section 9 of the SIM Reference Manual */
145  *DDRE = (unsigned char) 0xff;
146  *DDRF = (unsigned char) 0xfd;
147 
148  /* Port E and F Pin Assignment Register */
149  /*    see section 9 of the SIM Reference Manual */
150  *PEPAR = (unsigned char) 0;
151  *PFPAR = (unsigned char) 0;
152
153  /* end of SIM initalization code */
154  /* end include in ram_init.S */
155
156
157
158  /*
159   * Initialize RAM by copying the .data section out of ROM (if
160   * needed) and "zero-ing" the .bss section.
161   */
162  {
163    register char *src = _endtext;
164    register char *dst = _sdata;
165
166    if (_copy_data_from_rom)
167      /* ROM has data at end of text; copy it. */
168      while (dst < _edata)
169        *dst++ = *src++;
170   
171    /* Zero bss */
172    for (dst = __bss_start; dst< _end; dst++)
173      *dst = 0;
174  }
175
176  /*
177   * Initalize the board.
178   */
179  Spurious_Initialize();
180  console_init();
181
182  /*
183   * Execute main with arguments argv and environment env
184   */
185  main(1, __argv, __env);
186
187  reboot();
188}
189
190void reboot() {asm("trap #15");}
191
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