source: rtems/c/src/lib/libbsp/m68k/efi332/start332/start332.c @ 17f57736

4.104.114.84.95
Last change on this file since 17f57736 was 17f57736, checked in by Joel Sherrill <joel.sherrill@…>, on May 2, 1998 at 12:09:11 PM

removed warning for implicit declaration of boot_card()

  • Property mode set to 100644
File size: 5.9 KB
Line 
1/*
2 *  $Id
3 */
4
5#include <efi332.h>
6#include <sim.h>
7#define __START_C__
8#include "bsp.h"
9
10m68k_isr_entry M68Kvec[256];
11m68k_isr_entry vectors[256];
12char * const __argv[]= {"main", ""};
13char * const __env[]= {""};
14
15/*
16 *  This prototype really should have the noreturn attribute but
17 *  that causes a warning since it appears that the routine does
18 *  return.
19 *
20 *   void dumby_start ()  __attribute__ ((noreturn));
21 */
22
23void dumby_start ();
24void  dumby_start() {
25void  boot_card();
26
27  /* We need to by-pass the link instruction since the RAM chip-
28     select pins are not yet configured. */
29  asm volatile ( ".global start ;
30                  start:");
31
32  /* disable interrupts, load stack pointer */
33  asm volatile ( "oriw  #0x0700, %sr;
34                  moveal #M68Kvec, %a0;
35                  movec %a0, %vbr;
36                  movel  #_end, %d0;
37                  addl   " STACK_SIZE ",%d0;
38                  movel  %d0,%sp;
39                  link %a6, #0"
40                  );
41
42  /* include in ram_init.S */
43  /*
44   * Initalize the SIM module.
45   * The stack pointer is not usable until the RAM chip select lines
46   * are configured. The following code must remain inline.
47   */
48
49  /* Module Configuration Register */
50  /*    see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
51  *SIMCR = (unsigned short int) 
52    (FRZSW | FRZBM | SAM(0,8,SHEN) | (MM*SIM_MM) | SAM(SIM_IARB,0,IARB));
53
54  /* Synthesizer Control Register */
55  /*    see section(s) 4.8 */
56  /* end include in ram_init.S */
57  *SYNCR = (unsigned short int)
58    ( SAM(EFI_W,15,W) | SAM(0x0,14,X) | SAM(EFI_Y,8,Y) | STSIM );
59  while (! (*SYNCR & SLOCK));   /* protect from clock overshoot */
60  /* include in ram_init.S */
61  *SYNCR = (unsigned short int)
62    ( SAM(EFI_W,15,W) | SAM(EFI_X,14,X) | SAM(EFI_Y,8,Y) | STSIM );
63
64  /* System Protection Control Register */
65  /*    !!! can only write to once after reset !!! */
66  /*    see section 3.8.4 of the SIM Reference Manual */
67  *SYPCR = (unsigned char)( SAM(0x3,4,SWT) | HME | BME );
68
69  /* Periodic Interrupr Control Register */
70  /*    see section 3.8.2 of the SIM Reference Manual */
71  *PICR = (unsigned short int)
72    ( SAM(0,8,PIRQL) | SAM(EFI_PIV,0,PIV) );
73  /*     ^^^ zero disables interrupt, don't enable here or ram_init will
74         be wrong. It's enabled below. */
75
76  /* Periodic Interrupt Timer Register */
77  /*    see section 3.8.3 of the SIM Reference Manual */
78  *PITR = (unsigned short int)( SAM(0x09,0,PITM) );
79  /*    1.098mS interrupt */
80
81  /* Port C Data */
82  /*    load values before enabled */
83  *PORTC = (unsigned char) 0x0;
84
85  /* Chip-Select Base Address Register */
86  /*    see section 7 of the SIM Reference Manual */
87  *CSBARBT = (unsigned short int)
88    (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
89  *CSBAR0 = (unsigned short int)
90    (((0x000000 >> 8)&0xfff8) | BS_1M );   /* 1M bytes located at 0x0000 */
91  *CSBAR1 = (unsigned short int)
92    (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
93  *CSBAR2 = (unsigned short int)
94    (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0x80000 */
95  *CSBAR3 = (unsigned short int)         
96    (0xfff8 | BS_64K);                   /* AVEC interrupts */
97  *CSBAR10 = (unsigned short int)
98    (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
99
100  /* Chip-Select Options Registers */
101  /*    see section 7 of the SIM Reference Manual */
102  *CSORBT = (unsigned short int)
103    ( BothBytes | ReadWrite | SyncAS | WaitStates_13 | UserSupSpace );
104  *CSOR0 = (unsigned short int)
105    ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
106  *CSOR1 = (unsigned short int)
107    ( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
108  *CSOR2 = (unsigned short int)
109    ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
110  *CSOR3 = (unsigned short int)
111    ( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC );
112  *CSOR10 = (unsigned short int)
113    ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
114
115  /* Chip Select Pin Assignment Register 0 */
116  /*    see section 7 of the SIM Reference Manual */
117  *CSPAR0 = (unsigned short int)( 
118     SAM(DisOut,CS_5,0x3000) |  /* PC2 */
119     SAM(DisOut,CS_4,0x0c00) |  /* PC1 */
120     SAM(DisOut,CS_3,0x0300) |  /* AVEC (internally) */
121     SAM(CS16bit,CS_2,0x00c0)|  /* RAM UDS */
122     SAM(CS16bit,CS_1,0x0030)|  /* RAM LDS */
123     SAM(CS16bit,CS_0,0x000c)|  /* W/!R */
124     SAM(CS16bit,CSBOOT,0x0003) /* ROM DS */
125     );
126
127  /* Chip Select Pin Assignment Register 1 */
128  /*    see section 7 of the SIM Reference Manual */
129  *CSPAR1 = (unsigned short int)( 
130     SAM(CS16bit,CS_10,0x300)|  /* ECLK */
131     SAM(DisOut,CS_9,0x0c0) |   /* PC6 */
132     SAM(DisOut,CS_8,0x030) |   /* PC5 */
133     SAM(DisOut,CS_7,0x00c) |   /* PC4 */
134     SAM(DisOut,CS_6,0x003)     /* PC3 */
135     );
136
137  /* Port E and F Data Register */
138  /*    see section 9 of the SIM Reference Manual */
139  *PORTE0 = (unsigned char) 0;
140  *PORTF0 = (unsigned char) 0;
141
142  /* Port E and F Data Direction Register */
143  /*    see section 9 of the SIM Reference Manual */
144  *DDRE = (unsigned char) 0xff;
145  *DDRF = (unsigned char) 0xfd;
146 
147  /* Port E and F Pin Assignment Register */
148  /*    see section 9 of the SIM Reference Manual */
149  *PEPAR = (unsigned char) 0;
150  *PFPAR = (unsigned char) 0;
151
152  /* end of SIM initalization code */
153  /* end include in ram_init.S */
154
155
156
157  /*
158   * Initialize RAM by copying the .data section out of ROM (if
159   * needed) and "zero-ing" the .bss section.
160   */
161  {
162    register char *src = _endtext;
163    register char *dst = _sdata;
164
165    if (_copy_data_from_rom)
166      /* ROM has data at end of text; copy it. */
167      while (dst < _edata)
168        *dst++ = *src++;
169   
170    /* Zero bss */
171    for (dst = __bss_start; dst< _end; dst++)
172      *dst = 0;
173  }
174
175  /*
176   * Initalize the board.
177   */
178  Spurious_Initialize();
179  console_init();
180
181  /*
182   * Execute main with arguments argv and environment env
183   */
184  /* main(1, __argv, __env); */
185
186  boot_card();
187
188  reboot();
189}
190
191void reboot() {asm("trap #15");}
192
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