[6f9c75c3] | 1 | /* |
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| 2 | * $Id |
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| 3 | */ |
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| 4 | |
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[d0e126a6] | 5 | #include <efi332.h> |
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| 6 | #include <sim.h> |
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| 7 | #define __START_C__ |
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| 8 | #include "bsp.h" |
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| 9 | |
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| 10 | m68k_isr_entry M68Kvec[256]; |
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| 11 | m68k_isr_entry vectors[256]; |
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| 12 | char * const __argv[]= {"main", ""}; |
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[a902441a] | 13 | |
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| 14 | void boot_card(int argc, char * const argv[]); |
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[d0e126a6] | 15 | |
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[437366f] | 16 | /* |
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| 17 | * This prototype really should have the noreturn attribute but |
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[a902441a] | 18 | * that causes a warning. Not sure how to fix that. |
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[437366f] | 19 | */ |
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[a902441a] | 20 | /* void dumby_start () __attribute__ ((noreturn)); */ |
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[437366f] | 21 | void dumby_start (); |
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[a902441a] | 22 | |
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[d0e126a6] | 23 | void dumby_start() { |
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| 24 | |
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| 25 | /* We need to by-pass the link instruction since the RAM chip- |
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| 26 | select pins are not yet configured. */ |
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| 27 | asm volatile ( ".global start ; |
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| 28 | start:"); |
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| 29 | |
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| 30 | /* disable interrupts, load stack pointer */ |
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| 31 | asm volatile ( "oriw #0x0700, %sr; |
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| 32 | moveal #M68Kvec, %a0; |
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| 33 | movec %a0, %vbr; |
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| 34 | movel #_end, %d0; |
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| 35 | addl " STACK_SIZE ",%d0; |
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| 36 | movel %d0,%sp; |
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[a902441a] | 37 | movel %d0,%a6" |
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[d0e126a6] | 38 | ); |
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| 39 | |
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| 40 | /* include in ram_init.S */ |
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| 41 | /* |
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| 42 | * Initalize the SIM module. |
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| 43 | * The stack pointer is not usable until the RAM chip select lines |
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| 44 | * are configured. The following code must remain inline. |
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| 45 | */ |
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| 46 | |
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| 47 | /* Module Configuration Register */ |
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| 48 | /* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */ |
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| 49 | *SIMCR = (unsigned short int) |
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| 50 | (FRZSW | FRZBM | SAM(0,8,SHEN) | (MM*SIM_MM) | SAM(SIM_IARB,0,IARB)); |
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| 51 | |
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| 52 | /* Synthesizer Control Register */ |
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| 53 | /* see section(s) 4.8 */ |
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| 54 | /* end include in ram_init.S */ |
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| 55 | *SYNCR = (unsigned short int) |
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| 56 | ( SAM(EFI_W,15,W) | SAM(0x0,14,X) | SAM(EFI_Y,8,Y) | STSIM ); |
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| 57 | while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */ |
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| 58 | /* include in ram_init.S */ |
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| 59 | *SYNCR = (unsigned short int) |
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| 60 | ( SAM(EFI_W,15,W) | SAM(EFI_X,14,X) | SAM(EFI_Y,8,Y) | STSIM ); |
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| 61 | |
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| 62 | /* System Protection Control Register */ |
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| 63 | /* !!! can only write to once after reset !!! */ |
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| 64 | /* see section 3.8.4 of the SIM Reference Manual */ |
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| 65 | *SYPCR = (unsigned char)( SAM(0x3,4,SWT) | HME | BME ); |
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| 66 | |
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| 67 | /* Periodic Interrupr Control Register */ |
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| 68 | /* see section 3.8.2 of the SIM Reference Manual */ |
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| 69 | *PICR = (unsigned short int) |
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| 70 | ( SAM(0,8,PIRQL) | SAM(EFI_PIV,0,PIV) ); |
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| 71 | /* ^^^ zero disables interrupt, don't enable here or ram_init will |
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| 72 | be wrong. It's enabled below. */ |
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| 73 | |
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| 74 | /* Periodic Interrupt Timer Register */ |
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| 75 | /* see section 3.8.3 of the SIM Reference Manual */ |
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| 76 | *PITR = (unsigned short int)( SAM(0x09,0,PITM) ); |
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| 77 | /* 1.098mS interrupt */ |
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| 78 | |
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| 79 | /* Port C Data */ |
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| 80 | /* load values before enabled */ |
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| 81 | *PORTC = (unsigned char) 0x0; |
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| 82 | |
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| 83 | /* Chip-Select Base Address Register */ |
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| 84 | /* see section 7 of the SIM Reference Manual */ |
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| 85 | *CSBARBT = (unsigned short int) |
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| 86 | (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */ |
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| 87 | *CSBAR0 = (unsigned short int) |
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| 88 | (((0x000000 >> 8)&0xfff8) | BS_1M ); /* 1M bytes located at 0x0000 */ |
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| 89 | *CSBAR1 = (unsigned short int) |
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| 90 | (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */ |
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| 91 | *CSBAR2 = (unsigned short int) |
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[a902441a] | 92 | (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */ |
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[d0e126a6] | 93 | *CSBAR3 = (unsigned short int) |
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[a902441a] | 94 | (((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */ |
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| 95 | *CSBAR4 = (unsigned short int) |
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| 96 | (((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0xC0000 */ |
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| 97 | *CSBAR5 = (unsigned short int) |
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[d0e126a6] | 98 | (0xfff8 | BS_64K); /* AVEC interrupts */ |
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[a902441a] | 99 | #ifdef EFI332_v040b |
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| 100 | *CSBAR6 = (unsigned short int) |
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| 101 | (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */ |
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| 102 | *CSBAR8 = (unsigned short int) /* PCMCIA IOCS */ |
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| 103 | (((0x0c0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xc0000 */ |
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| 104 | *CSBAR9 = (unsigned short int) /* PCMCIA MEMCS */ |
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| 105 | (((0x0D0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xd0000 */ |
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| 106 | #else /* EFI332_v040b */ |
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[d0e126a6] | 107 | *CSBAR10 = (unsigned short int) |
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| 108 | (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */ |
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[a902441a] | 109 | #endif /* EFI332_v040b */ |
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[d0e126a6] | 110 | |
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| 111 | /* Chip-Select Options Registers */ |
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| 112 | /* see section 7 of the SIM Reference Manual */ |
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[a902441a] | 113 | #ifdef FLASHWRITE |
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| 114 | *CSORBT = (unsigned short int) |
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| 115 | ( BothBytes | ReadWrite | SyncAS | WaitStates_2 | UserSupSpace ); |
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| 116 | #else /* FLASHWRITE */ |
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[d0e126a6] | 117 | *CSORBT = (unsigned short int) |
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[a902441a] | 118 | ( BothBytes | ReadOnly | SyncAS | WaitStates_2 | UserSupSpace ); |
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| 119 | #endif /* FLASHWRITE */ |
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[d0e126a6] | 120 | *CSOR0 = (unsigned short int) |
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| 121 | ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); |
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| 122 | *CSOR1 = (unsigned short int) |
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| 123 | ( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); |
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| 124 | *CSOR2 = (unsigned short int) |
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| 125 | ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); |
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| 126 | *CSOR3 = (unsigned short int) |
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[a902441a] | 127 | ( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); |
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| 128 | *CSOR4 = (unsigned short int) |
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| 129 | ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); |
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| 130 | *CSOR5 = (unsigned short int) |
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[d0e126a6] | 131 | ( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC ); |
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[a902441a] | 132 | #ifdef EFI332_v040b |
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| 133 | *CSOR6 = (unsigned short int) |
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| 134 | ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); |
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| 135 | *CSOR8 = (unsigned short int) |
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| 136 | ( BothBytes | ReadWrite | SyncAS | External | UserSupSpace ); |
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| 137 | *CSOR9 = (unsigned short int) |
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| 138 | ( BothBytes | ReadWrite | SyncAS | External | UserSupSpace ); |
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| 139 | #else /* EFI332_v040b */ |
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[d0e126a6] | 140 | *CSOR10 = (unsigned short int) |
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| 141 | ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); |
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[a902441a] | 142 | #endif /* EFI332_v040b */ |
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[d0e126a6] | 143 | |
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| 144 | /* Chip Select Pin Assignment Register 0 */ |
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| 145 | /* see section 7 of the SIM Reference Manual */ |
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| 146 | *CSPAR0 = (unsigned short int)( |
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[a902441a] | 147 | SAM(DisOut,CS_5,0x3000) | /* AVEC (internally) */ |
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| 148 | SAM(CS16bit,CS_4,0x0c00) | /* RAM UDS, bank2 */ |
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| 149 | SAM(CS16bit,CS_3,0x0300) | /* RAM LDS, bank2 */ |
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| 150 | SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS, bank1 */ |
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| 151 | SAM(CS16bit,CS_1,0x0030)| /* RAM LDS, bank1 */ |
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[d0e126a6] | 152 | SAM(CS16bit,CS_0,0x000c)| /* W/!R */ |
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[a902441a] | 153 | SAM(CS16bit,CSBOOT,0x0003) /* ROM CS */ |
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[d0e126a6] | 154 | ); |
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| 155 | |
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| 156 | /* Chip Select Pin Assignment Register 1 */ |
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| 157 | /* see section 7 of the SIM Reference Manual */ |
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[a902441a] | 158 | #ifdef EFI332_v040b |
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| 159 | *CSPAR1 = (unsigned short int)( |
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| 160 | SAM(DisOut,CS_10,0x300)| /* ECLK */ |
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| 161 | SAM(CS16bit,CS_9,0x0c0) | /* PCMCIA MEMCS */ |
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| 162 | SAM(CS16bit,CS_8,0x030) | /* PCMCIA IOCS */ |
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| 163 | SAM(DisOut,CS_7,0x00c) | /* PC4 */ |
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| 164 | SAM(CS16bit,CS_6,0x003) /* ROM !OE */ |
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| 165 | ); |
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| 166 | #else /* EFI332_v040b */ |
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[d0e126a6] | 167 | *CSPAR1 = (unsigned short int)( |
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[a902441a] | 168 | SAM(CS16bit,CS_10,0x300)| /* ROM !OE */ |
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[d0e126a6] | 169 | SAM(DisOut,CS_9,0x0c0) | /* PC6 */ |
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| 170 | SAM(DisOut,CS_8,0x030) | /* PC5 */ |
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| 171 | SAM(DisOut,CS_7,0x00c) | /* PC4 */ |
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| 172 | SAM(DisOut,CS_6,0x003) /* PC3 */ |
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| 173 | ); |
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[a902441a] | 174 | #endif /* EFI332_v040b */ |
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[d0e126a6] | 175 | |
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| 176 | /* Port E and F Data Register */ |
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| 177 | /* see section 9 of the SIM Reference Manual */ |
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| 178 | *PORTE0 = (unsigned char) 0; |
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| 179 | *PORTF0 = (unsigned char) 0; |
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| 180 | |
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| 181 | /* Port E and F Data Direction Register */ |
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| 182 | /* see section 9 of the SIM Reference Manual */ |
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| 183 | *DDRE = (unsigned char) 0xff; |
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| 184 | *DDRF = (unsigned char) 0xfd; |
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| 185 | |
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| 186 | /* Port E and F Pin Assignment Register */ |
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| 187 | /* see section 9 of the SIM Reference Manual */ |
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| 188 | *PEPAR = (unsigned char) 0; |
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| 189 | *PFPAR = (unsigned char) 0; |
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| 190 | |
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| 191 | /* end of SIM initalization code */ |
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| 192 | /* end include in ram_init.S */ |
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| 193 | |
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| 194 | |
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| 195 | |
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| 196 | /* |
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| 197 | * Initialize RAM by copying the .data section out of ROM (if |
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| 198 | * needed) and "zero-ing" the .bss section. |
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| 199 | */ |
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| 200 | { |
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| 201 | register char *src = _endtext; |
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| 202 | register char *dst = _sdata; |
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| 203 | |
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| 204 | if (_copy_data_from_rom) |
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| 205 | /* ROM has data at end of text; copy it. */ |
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| 206 | while (dst < _edata) |
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| 207 | *dst++ = *src++; |
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| 208 | |
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| 209 | /* Zero bss */ |
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| 210 | for (dst = __bss_start; dst< _end; dst++) |
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| 211 | *dst = 0; |
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| 212 | } |
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| 213 | |
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| 214 | /* |
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| 215 | * Initalize the board. |
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| 216 | */ |
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| 217 | Spurious_Initialize(); |
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| 218 | console_init(); |
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| 219 | |
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| 220 | /* |
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[a902441a] | 221 | * Execute main with arguments argc and agrv. |
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[d0e126a6] | 222 | */ |
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[a902441a] | 223 | boot_card(1,__argv); |
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[d0e126a6] | 224 | reboot(); |
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| 225 | |
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[a902441a] | 226 | } |
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[d0e126a6] | 227 | |
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