[6f9c75c3] | 1 | /* |
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| 2 | * $Id |
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| 3 | */ |
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| 4 | |
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[d0e126a6] | 5 | #include <efi332.h> |
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| 6 | #include <sim.h> |
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| 7 | #define __START_C__ |
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| 8 | #include "bsp.h" |
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| 9 | |
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| 10 | m68k_isr_entry M68Kvec[256]; |
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| 11 | m68k_isr_entry vectors[256]; |
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| 12 | char * const __argv[]= {"main", ""}; |
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| 13 | char * const __env[]= {""}; |
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| 14 | |
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[437366f] | 15 | /* |
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| 16 | * This prototype really should have the noreturn attribute but |
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| 17 | * that causes a warning since it appears that the routine does |
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| 18 | * return. |
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| 19 | * |
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| 20 | * void dumby_start () __attribute__ ((noreturn)); |
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| 21 | */ |
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| 22 | |
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| 23 | void dumby_start (); |
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[d0e126a6] | 24 | void dumby_start() { |
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[17f57736] | 25 | void boot_card(); |
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[d0e126a6] | 26 | |
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| 27 | /* We need to by-pass the link instruction since the RAM chip- |
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| 28 | select pins are not yet configured. */ |
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| 29 | asm volatile ( ".global start ; |
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| 30 | start:"); |
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| 31 | |
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| 32 | /* disable interrupts, load stack pointer */ |
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| 33 | asm volatile ( "oriw #0x0700, %sr; |
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| 34 | moveal #M68Kvec, %a0; |
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| 35 | movec %a0, %vbr; |
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| 36 | movel #_end, %d0; |
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| 37 | addl " STACK_SIZE ",%d0; |
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| 38 | movel %d0,%sp; |
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| 39 | link %a6, #0" |
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| 40 | ); |
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| 41 | |
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| 42 | /* include in ram_init.S */ |
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| 43 | /* |
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| 44 | * Initalize the SIM module. |
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| 45 | * The stack pointer is not usable until the RAM chip select lines |
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| 46 | * are configured. The following code must remain inline. |
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| 47 | */ |
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| 48 | |
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| 49 | /* Module Configuration Register */ |
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| 50 | /* see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */ |
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| 51 | *SIMCR = (unsigned short int) |
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| 52 | (FRZSW | FRZBM | SAM(0,8,SHEN) | (MM*SIM_MM) | SAM(SIM_IARB,0,IARB)); |
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| 53 | |
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| 54 | /* Synthesizer Control Register */ |
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| 55 | /* see section(s) 4.8 */ |
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| 56 | /* end include in ram_init.S */ |
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| 57 | *SYNCR = (unsigned short int) |
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| 58 | ( SAM(EFI_W,15,W) | SAM(0x0,14,X) | SAM(EFI_Y,8,Y) | STSIM ); |
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| 59 | while (! (*SYNCR & SLOCK)); /* protect from clock overshoot */ |
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| 60 | /* include in ram_init.S */ |
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| 61 | *SYNCR = (unsigned short int) |
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| 62 | ( SAM(EFI_W,15,W) | SAM(EFI_X,14,X) | SAM(EFI_Y,8,Y) | STSIM ); |
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| 63 | |
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| 64 | /* System Protection Control Register */ |
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| 65 | /* !!! can only write to once after reset !!! */ |
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| 66 | /* see section 3.8.4 of the SIM Reference Manual */ |
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| 67 | *SYPCR = (unsigned char)( SAM(0x3,4,SWT) | HME | BME ); |
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| 68 | |
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| 69 | /* Periodic Interrupr Control Register */ |
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| 70 | /* see section 3.8.2 of the SIM Reference Manual */ |
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| 71 | *PICR = (unsigned short int) |
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| 72 | ( SAM(0,8,PIRQL) | SAM(EFI_PIV,0,PIV) ); |
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| 73 | /* ^^^ zero disables interrupt, don't enable here or ram_init will |
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| 74 | be wrong. It's enabled below. */ |
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| 75 | |
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| 76 | /* Periodic Interrupt Timer Register */ |
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| 77 | /* see section 3.8.3 of the SIM Reference Manual */ |
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| 78 | *PITR = (unsigned short int)( SAM(0x09,0,PITM) ); |
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| 79 | /* 1.098mS interrupt */ |
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| 80 | |
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| 81 | /* Port C Data */ |
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| 82 | /* load values before enabled */ |
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| 83 | *PORTC = (unsigned char) 0x0; |
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| 84 | |
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| 85 | /* Chip-Select Base Address Register */ |
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| 86 | /* see section 7 of the SIM Reference Manual */ |
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| 87 | *CSBARBT = (unsigned short int) |
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| 88 | (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */ |
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| 89 | *CSBAR0 = (unsigned short int) |
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| 90 | (((0x000000 >> 8)&0xfff8) | BS_1M ); /* 1M bytes located at 0x0000 */ |
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| 91 | *CSBAR1 = (unsigned short int) |
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| 92 | (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */ |
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| 93 | *CSBAR2 = (unsigned short int) |
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| 94 | (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256 bytes located at 0x80000 */ |
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| 95 | *CSBAR3 = (unsigned short int) |
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| 96 | (0xfff8 | BS_64K); /* AVEC interrupts */ |
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| 97 | *CSBAR10 = (unsigned short int) |
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| 98 | (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */ |
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| 99 | |
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| 100 | /* Chip-Select Options Registers */ |
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| 101 | /* see section 7 of the SIM Reference Manual */ |
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| 102 | *CSORBT = (unsigned short int) |
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| 103 | ( BothBytes | ReadWrite | SyncAS | WaitStates_13 | UserSupSpace ); |
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| 104 | *CSOR0 = (unsigned short int) |
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| 105 | ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); |
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| 106 | *CSOR1 = (unsigned short int) |
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| 107 | ( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); |
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| 108 | *CSOR2 = (unsigned short int) |
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| 109 | ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace ); |
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| 110 | *CSOR3 = (unsigned short int) |
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| 111 | ( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC ); |
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| 112 | *CSOR10 = (unsigned short int) |
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| 113 | ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace ); |
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| 114 | |
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| 115 | /* Chip Select Pin Assignment Register 0 */ |
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| 116 | /* see section 7 of the SIM Reference Manual */ |
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| 117 | *CSPAR0 = (unsigned short int)( |
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| 118 | SAM(DisOut,CS_5,0x3000) | /* PC2 */ |
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| 119 | SAM(DisOut,CS_4,0x0c00) | /* PC1 */ |
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| 120 | SAM(DisOut,CS_3,0x0300) | /* AVEC (internally) */ |
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| 121 | SAM(CS16bit,CS_2,0x00c0)| /* RAM UDS */ |
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| 122 | SAM(CS16bit,CS_1,0x0030)| /* RAM LDS */ |
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| 123 | SAM(CS16bit,CS_0,0x000c)| /* W/!R */ |
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| 124 | SAM(CS16bit,CSBOOT,0x0003) /* ROM DS */ |
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| 125 | ); |
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| 126 | |
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| 127 | /* Chip Select Pin Assignment Register 1 */ |
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| 128 | /* see section 7 of the SIM Reference Manual */ |
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| 129 | *CSPAR1 = (unsigned short int)( |
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| 130 | SAM(CS16bit,CS_10,0x300)| /* ECLK */ |
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| 131 | SAM(DisOut,CS_9,0x0c0) | /* PC6 */ |
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| 132 | SAM(DisOut,CS_8,0x030) | /* PC5 */ |
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| 133 | SAM(DisOut,CS_7,0x00c) | /* PC4 */ |
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| 134 | SAM(DisOut,CS_6,0x003) /* PC3 */ |
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| 135 | ); |
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| 136 | |
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| 137 | /* Port E and F Data Register */ |
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| 138 | /* see section 9 of the SIM Reference Manual */ |
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| 139 | *PORTE0 = (unsigned char) 0; |
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| 140 | *PORTF0 = (unsigned char) 0; |
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| 141 | |
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| 142 | /* Port E and F Data Direction Register */ |
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| 143 | /* see section 9 of the SIM Reference Manual */ |
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| 144 | *DDRE = (unsigned char) 0xff; |
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| 145 | *DDRF = (unsigned char) 0xfd; |
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| 146 | |
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| 147 | /* Port E and F Pin Assignment Register */ |
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| 148 | /* see section 9 of the SIM Reference Manual */ |
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| 149 | *PEPAR = (unsigned char) 0; |
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| 150 | *PFPAR = (unsigned char) 0; |
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| 151 | |
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| 152 | /* end of SIM initalization code */ |
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| 153 | /* end include in ram_init.S */ |
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| 154 | |
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| 155 | |
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| 156 | |
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| 157 | /* |
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| 158 | * Initialize RAM by copying the .data section out of ROM (if |
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| 159 | * needed) and "zero-ing" the .bss section. |
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| 160 | */ |
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| 161 | { |
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| 162 | register char *src = _endtext; |
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| 163 | register char *dst = _sdata; |
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| 164 | |
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| 165 | if (_copy_data_from_rom) |
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| 166 | /* ROM has data at end of text; copy it. */ |
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| 167 | while (dst < _edata) |
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| 168 | *dst++ = *src++; |
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| 169 | |
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| 170 | /* Zero bss */ |
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| 171 | for (dst = __bss_start; dst< _end; dst++) |
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| 172 | *dst = 0; |
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| 173 | } |
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| 174 | |
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| 175 | /* |
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| 176 | * Initalize the board. |
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| 177 | */ |
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| 178 | Spurious_Initialize(); |
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| 179 | console_init(); |
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| 180 | |
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| 181 | /* |
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| 182 | * Execute main with arguments argv and environment env |
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| 183 | */ |
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[e2a2ec60] | 184 | /* main(1, __argv, __env); */ |
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| 185 | |
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| 186 | boot_card(); |
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[d0e126a6] | 187 | |
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| 188 | reboot(); |
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| 189 | } |
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| 190 | |
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| 191 | void reboot() {asm("trap #15");} |
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| 192 | |
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