source: rtems/c/src/lib/libbsp/m68k/efi332/start/start.c @ 50bb7627

4.104.114.84.95
Last change on this file since 50bb7627 was 50bb7627, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 12, 2000 at 12:56:07 PM

2000-10-12 John S Gwynne <jgwynne@…>

  • start/start.c: Modified to support generation of ram_init.
  • start/ram_init.ld, BSP/start/ram_init.sed: New files. These changes enable RTEMS to automatically generate the ram_init file used by gdb with the BDM patches. The 332 has on-board chip select lines (for RAM and FLASH) that must be configured before use of these peripherals. These patches parse data from start.c where the chip select lines are configured in the runtime executable and automatically generates the gdb initialization file using the same settings. A great time saver. A similar file, ram_init_FW (flash writable), is also generated that the flash programming tool uses.
  • start/Makefile.am: Modified to support above.
  • CPU/sim.h: Modified to support above.
  • startup/except_vect_332_ROM.S: Moved to start so it would not be included in libbsp.a. Moving it to start ensures it is available as a single object file.
  • start/except_vect_332_ROM.S: Moved from startup.
  • startup/linkcmds, startup/linkcmds_ROM: Fixes to the memory map shown in the comments.
  • Property mode set to 100644
File size: 7.6 KB
Line 
1/*
2 *  $Id
3 */
4
5#include <efi332.h>
6#include <sim.h>
7#define __START_C__
8#include "bsp.h"
9
10m68k_isr_entry M68Kvec[256];
11m68k_isr_entry vectors[256];
12char * const __argv[]= {"main", ""};
13
14void  boot_card(int argc, char * const argv[]);
15
16/*
17 *  This prototype really should have the noreturn attribute but
18 *  that causes a warning. Not sure how to fix that.
19 */
20/* void dumby_start ()  __attribute__ ((noreturn)); */
21void dumby_start ();
22
23void  dumby_start() {
24
25  /* We need to by-pass the link instruction since the RAM chip-
26     select pins are not yet configured. */
27  asm volatile ( ".global start ;
28                  start:");
29
30  /* disable interrupts, load stack pointer */
31  asm volatile ( "oriw  #0x0700, %sr;
32                  moveal #M68Kvec, %a0;
33                  movec %a0, %vbr;
34                  movel  #end, %d0;
35                  addl   " STACK_SIZE ",%d0;
36                  movel  %d0,%sp;
37                  movel  %d0,%a6"
38                  );
39
40  /* include in ram_init.S */
41  /*
42   * Initalize the SIM module.
43   * The stack pointer is not usable until the RAM chip select lines
44   * are configured. The following code must remain inline.
45   */
46
47  /* Module Configuration Register */
48  /*    see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
49  *SIMCR = (unsigned short int) 
50    (FRZSW | FRZBM | SAM(0,8,SHEN) | (MM*SIM_MM) | SAM(SIM_IARB,0,IARB));
51
52  /* Synthesizer Control Register */
53  /*    see section(s) 4.8 */
54  /* end include in ram_init.S */
55  *SYNCR = (unsigned short int)
56    ( SAM(EFI_W,15,VCO) | SAM(0x0,14,PRESCALE) | SAM(EFI_Y,8,COUNTER) | STSIM );
57  while (! (*SYNCR & SLOCK));   /* protect from clock overshoot */
58  /* include in ram_init.S */
59  *SYNCR = (unsigned short int)
60    ( SAM(EFI_W,15,VCO) | SAM(EFI_X,14,PRESCALE) | SAM(EFI_Y,8,COUNTER) | STSIM );
61
62  /* System Protection Control Register */
63  /*    !!! can only write to once after reset !!! */
64  /*    see section 3.8.4 of the SIM Reference Manual */
65  *SYPCR = (unsigned char)( SAM(0x3,4,SWT) | HME | BME );
66
67  /* Periodic Interrupr Control Register */
68  /*    see section 3.8.2 of the SIM Reference Manual */
69  *PICR = (unsigned short int)
70    ( SAM(0,8,PIRQL) | SAM(EFI_PIV,0,PIV) );
71  /*     ^^^ zero disables interrupt, don't enable here or ram_init will
72         be wrong. It's enabled below. */
73
74  /* Periodic Interrupt Timer Register */
75  /*    see section 3.8.3 of the SIM Reference Manual */
76  *PITR = (unsigned short int)( SAM(0x09,0,PITM) );
77  /*    1.098mS interrupt */
78
79  /* Port C Data */
80  /*    load values before enabled */
81  *PORTC = (unsigned char) 0x0;
82
83  /* Chip-Select Base Address Register */
84  /*    see section 7 of the SIM Reference Manual */
85  *CSBARBT = (unsigned short int)
86    (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
87  *CSBAR0 = (unsigned short int)
88    (((0x000000 >> 8)&0xfff8) | BS_1M );   /* 1M bytes located at 0x0000 */
89  *CSBAR1 = (unsigned short int)
90    (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
91  *CSBAR2 = (unsigned short int)
92    (((0x080000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0x80000 */
93  *CSBAR3 = (unsigned short int)         
94    (((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */
95  *CSBAR4 = (unsigned short int)
96    (((0x0C0000 >> 8)&0xfff8) | BS_256K ); /* 256k bytes located at 0xC0000 */
97  *CSBAR5 = (unsigned short int)         
98    (0xfff8 | BS_64K);                   /* AVEC interrupts */
99#ifdef EFI332_v040b
100  *CSBAR6 = (unsigned short int)
101    (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
102  *CSBAR8 = (unsigned short int) /* PCMCIA IOCS */
103    (((0x0c0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xc0000 */
104  *CSBAR9 = (unsigned short int) /* PCMCIA MEMCS */
105    (((0x0D0000 >> 8)&0xfff8) | BS_64K ); /* 64k bytes located at 0xd0000 */
106#else /* EFI332_v040b */
107  *CSBAR10 = (unsigned short int)
108    (((0x000000 >> 8)&0xfff8) | BS_512K ); /* 512k bytes located at 0x0000 */
109#endif /* EFI332_v040b */
110
111  /* Chip-Select Options Registers */
112  /*    see section 7 of the SIM Reference Manual */
113#ifdef FLASHWRITE
114  *CSORBT = (unsigned short int)
115    ( BothBytes | ReadWrite | SyncAS | WaitStates_2 | UserSupSpace );
116#else /* FLASHWRITE */
117  *CSORBT = (unsigned short int)
118    ( BothBytes | ReadOnly | SyncAS | WaitStates_0 | UserSupSpace );
119#endif /* FLASHWRITE */
120  *CSOR0 = (unsigned short int)
121    ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
122  *CSOR1 = (unsigned short int)
123    ( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
124  *CSOR2 = (unsigned short int)
125    ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
126  *CSOR3 = (unsigned short int)
127    ( LowerByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
128  *CSOR4 = (unsigned short int)
129    ( UpperByte | ReadWrite | SyncAS | FastTerm | UserSupSpace );
130  *CSOR5 = (unsigned short int)
131    ( BothBytes | ReadWrite | SyncAS | CPUSpace | IPLevel_any | AVEC );
132#ifdef EFI332_v040b
133  *CSOR6 = (unsigned short int)
134    ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
135  *CSOR8 = (unsigned short int)
136    ( BothBytes | ReadWrite | SyncAS | External | UserSupSpace );
137  *CSOR9 = (unsigned short int)
138    ( BothBytes | ReadWrite | SyncAS | External | UserSupSpace );
139#else /* EFI332_v040b */
140  *CSOR10 = (unsigned short int)
141    ( BothBytes | ReadOnly | SyncAS | External | UserSupSpace );
142#endif /* EFI332_v040b */
143
144  /* Chip Select Pin Assignment Register 0 */
145  /*    see section 7 of the SIM Reference Manual */
146  *CSPAR0 = (unsigned short int)( 
147     SAM(DisOut,CS_5,0x3000) |  /* AVEC (internally) */
148     SAM(CS16bit,CS_4,0x0c00) | /* RAM UDS, bank2 */
149     SAM(CS16bit,CS_3,0x0300) | /* RAM LDS, bank2 */
150     SAM(CS16bit,CS_2,0x00c0)|  /* RAM UDS, bank1 */
151     SAM(CS16bit,CS_1,0x0030)|  /* RAM LDS, bank1 */
152     SAM(CS16bit,CS_0,0x000c)|  /* W/!R */
153     SAM(CS16bit,CSBOOT,0x0003) /* ROM CS */
154     );
155
156  /* Chip Select Pin Assignment Register 1 */
157  /*    see section 7 of the SIM Reference Manual */
158#ifdef EFI332_v040b
159  *CSPAR1 = (unsigned short int)( 
160     SAM(DisOut,CS_10,0x300)|   /* ECLK */
161     SAM(CS16bit,CS_9,0x0c0) |  /* PCMCIA MEMCS */
162     SAM(CS16bit,CS_8,0x030) |  /* PCMCIA IOCS */
163     SAM(DisOut,CS_7,0x00c) |   /* PC4 */
164     SAM(CS16bit,CS_6,0x003)    /* ROM !OE */
165     );
166#else /* EFI332_v040b */
167  *CSPAR1 = (unsigned short int)( 
168     SAM(CS16bit,CS_10,0x300)|  /* ROM !OE */
169     SAM(DisOut,CS_9,0x0c0) |   /* PC6 */
170     SAM(DisOut,CS_8,0x030) |   /* PC5 */
171     SAM(DisOut,CS_7,0x00c) |   /* PC4 */
172     SAM(DisOut,CS_6,0x003)     /* PC3 */
173     );
174#endif /* EFI332_v040b */
175
176  /* Port E and F Data Register */
177  /*    see section 9 of the SIM Reference Manual */
178  *PORTE0 = (unsigned char) 0;
179  *PORTF0 = (unsigned char) 0;
180
181  /* Port E and F Data Direction Register */
182  /*    see section 9 of the SIM Reference Manual */
183  *DDRE = (unsigned char) 0xff;
184  *DDRF = (unsigned char) 0xfd;
185 
186  /* Port E and F Pin Assignment Register */
187  /*    see section 9 of the SIM Reference Manual */
188  *PEPAR = (unsigned char) 0xc3; /* siz1|siz0|dsack1|dsack0 */
189  *PFPAR = (unsigned char) 0;
190
191  /* end of SIM initalization code */
192  /* end include in ram_init.S */
193
194
195
196  /*
197   * Initialize RAM by copying the .data section out of ROM (if
198   * needed) and "zero-ing" the .bss section.
199   */
200  {
201    register char *src = _etext;
202    register char *dst = _copy_start;
203
204    if (_copy_data_from_rom)
205      /* ROM has data at end of text; copy it. */
206      while (dst < _edata)
207        *dst++ = *src++;
208   
209    /* Zero bss */
210    for (dst = _clear_start; dst< end; dst++)
211      *dst = 0;
212  }
213
214  /*
215   * Initalize the board.
216   */
217  Spurious_Initialize();
218  console_init();
219
220  /*
221   * Execute main with arguments argc and agrv.
222   */
223  boot_card(1,__argv);
224  reboot();
225
226}
227
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