[ac7d5ef0] | 1 | /* bsp.h |
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| 2 | * |
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| 3 | * This include file contains all DMV152 board IO definitions. |
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| 4 | * |
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[08311cc3] | 5 | * COPYRIGHT (c) 1989-1999. |
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[ac7d5ef0] | 6 | * On-Line Applications Research Corporation (OAR). |
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| 7 | * |
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[98e4ebf5] | 8 | * The license and distribution terms for this file may be |
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| 9 | * found in the file LICENSE in this distribution or at |
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[9980062] | 10 | * http://www.rtems.com/license/LICENSE. |
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[ac7d5ef0] | 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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| 14 | |
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| 15 | #ifndef __DMV152_h |
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| 16 | #define __DMV152_h |
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| 17 | |
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| 18 | #ifdef __cplusplus |
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| 19 | extern "C" { |
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| 20 | #endif |
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| 21 | |
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[ebf3adc] | 22 | #include <bspopts.h> |
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| 23 | |
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[ac7d5ef0] | 24 | #include <rtems.h> |
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[c2e9632] | 25 | #include <rtems/console.h> |
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| 26 | #include <rtems/clockdrv.h> |
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| 27 | #include <rtems/iosupp.h> |
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| 28 | #include <rtems/vmeintr.h> |
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[5e6d901] | 29 | #include <rtems/zilog/z8530.h> |
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| 30 | #include <rtems/zilog/z8536.h> |
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[ac7d5ef0] | 31 | |
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[df49c60] | 32 | /* |
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| 33 | * confdefs.h overrides for this BSP: |
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| 34 | * - number of termios serial ports (defaults to 1) |
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| 35 | * - Interrupt stack space is not minimum if defined. |
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| 36 | */ |
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| 37 | |
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| 38 | /* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */ |
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| 39 | #define CONFIGURE_INTERRUPT_STACK_MEMORY (4 * 1024) |
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| 40 | |
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| 41 | /* |
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| 42 | * confdefs.h overrides for this BSP: |
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| 43 | * - termios serial ports (defaults to 1) |
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| 44 | * - Interrupt stack space is not minimum if defined. |
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| 45 | */ |
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| 46 | |
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| 47 | #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 |
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| 48 | /* #define CONFIGURE_INTERRUPT_STACK_MEMORY (TBD * 1024) */ |
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[6128a4a] | 49 | |
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[ac7d5ef0] | 50 | /* |
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| 51 | * Simple spin delay in microsecond units for device drivers. |
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| 52 | * This is very dependent on the clock speed of the target. |
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| 53 | */ |
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| 54 | |
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[cf282090] | 55 | #define rtems_bsp_delay( microseconds ) \ |
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[0f458a3] | 56 | { register uint32_t _delay=(microseconds); \ |
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| 57 | register uint32_t _tmp=123; \ |
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[ac7d5ef0] | 58 | asm volatile( "0: \ |
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| 59 | nbcd %0 ; \ |
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| 60 | nbcd %0 ; \ |
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| 61 | dbf %1,0b" \ |
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| 62 | : "=d" (_tmp), "=d" (_delay) \ |
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| 63 | : "0" (_tmp), "1" (_delay) ); \ |
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| 64 | } |
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| 65 | |
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| 66 | /* macros */ |
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| 67 | |
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| 68 | #undef Z8x36_STATE0 |
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| 69 | #undef Z8x36_WRITE |
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| 70 | #undef Z8x36_READ |
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| 71 | |
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| 72 | #define Z8x36_STATE0 ( z8536 ) \ |
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| 73 | { char *garbage; \ |
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| 74 | (garbage) = *(VOL8(z8536+0x7)) \ |
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| 75 | } |
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| 76 | |
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| 77 | #define Z8x36_WRITE( z8536, reg, data ) \ |
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| 78 | *(VOL8(z8536+0x7)) = (reg); \ |
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| 79 | *(VOL8(z8536+0x7)) = (data) |
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| 80 | |
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| 81 | #define Z8x36_READ( z8536, reg, data ) \ |
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| 82 | *(VOL8(z8536+0x7)) = (reg); \ |
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| 83 | (data) = *(VOL8(z8536+0x7)) |
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| 84 | |
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| 85 | /* |
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| 86 | * ACC Register Addresses |
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| 87 | */ |
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| 88 | |
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| 89 | #define ACC_BASE 0x0D000000 |
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| 90 | |
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[0f458a3] | 91 | #define ACC_STAT0 ((volatile uint8_t*) (ACC_BASE + 0x00)) |
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| 92 | #define ACC_STAT1 ((volatile uint8_t*) (ACC_BASE + 0x01)) |
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| 93 | #define ACC_GENCTL ((volatile uint8_t*) (ACC_BASE + 0x02)) |
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| 94 | #define ACC_VINT ((volatile uint8_t*) (ACC_BASE + 0x03)) |
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| 95 | #define ACC_VREQ ((volatile uint8_t*) (ACC_BASE + 0x04)) |
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| 96 | #define ACC_VARB ((volatile uint8_t*) (ACC_BASE + 0x05)) |
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| 97 | #define ACC_ID ((volatile uint8_t*) (ACC_BASE + 0x06)) |
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| 98 | #define ACC_CTL2 ((volatile uint8_t*) (ACC_BASE + 0x07)) |
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| 99 | #define ACC_7IS ((volatile uint8_t*) (ACC_BASE + 0x08)) |
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| 100 | #define ACC_LIS ((volatile uint8_t*) (ACC_BASE + 0x09)) |
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| 101 | #define ACC_7IE ((volatile uint8_t*) (ACC_BASE + 0x0A)) |
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| 102 | #define ACC_LIE ((volatile uint8_t*) (ACC_BASE + 0x0B)) |
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| 103 | #define ACC_VIE ((volatile uint8_t*) (ACC_BASE + 0x0C)) |
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| 104 | #define ACC_IC10 ((volatile uint8_t*) (ACC_BASE + 0x0D)) |
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| 105 | #define ACC_IC32 ((volatile uint8_t*) (ACC_BASE + 0x0E)) |
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| 106 | #define ACC_IC54 ((volatile uint8_t*) (ACC_BASE + 0x0F)) |
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[ac7d5ef0] | 107 | |
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| 108 | /* constants */ |
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| 109 | |
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| 110 | #define TIMER 0x0c000000 |
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| 111 | #define TIMER_VECTOR 0x4D |
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| 112 | |
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[edd1329f] | 113 | #define CONSOLE_CONTROL_A 0x0C800005 |
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| 114 | #define CONSOLE_DATA_A 0x0C800007 |
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| 115 | #define CONSOLE_CONTROL_B 0x0C800001 |
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| 116 | #define CONSOLE_DATA_B 0x0C800003 |
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[ac7d5ef0] | 117 | |
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| 118 | /* Structures */ |
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| 119 | |
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[edd1329f] | 120 | /* none */ |
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[ac7d5ef0] | 121 | |
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| 122 | /* miscellaneous stuff assumed to exist */ |
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| 123 | |
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| 124 | extern rtems_configuration_table BSP_Configuration; |
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| 125 | |
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[497428a2] | 126 | extern m68k_isr_entry M68Kvec[]; /* vector table address */ |
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[ac7d5ef0] | 127 | |
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[3a4ae6c] | 128 | /* |
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| 129 | * Device Driver Table Entries |
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| 130 | */ |
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| 131 | |
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| 132 | /* |
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| 133 | * NOTE: Use the standard Console driver entry |
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| 134 | */ |
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[6128a4a] | 135 | |
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[3a4ae6c] | 136 | /* |
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| 137 | * NOTE: Use the standard Clock driver entry |
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| 138 | */ |
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| 139 | |
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[ac7d5ef0] | 140 | /* functions */ |
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| 141 | |
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| 142 | void bsp_cleanup( void ); |
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| 143 | |
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[497428a2] | 144 | m68k_isr_entry set_vector( |
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[ac7d5ef0] | 145 | rtems_isr_entry handler, |
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| 146 | rtems_vector_number vector, |
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| 147 | int type |
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| 148 | ); |
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| 149 | |
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| 150 | #ifdef __cplusplus |
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| 151 | } |
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| 152 | #endif |
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| 153 | |
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| 154 | #endif |
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| 155 | /* end of include file */ |
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