[ac7d5ef0] | 1 | /* Clock_init() |
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| 2 | * |
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| 3 | * This routine initializes the Z80386 1 on the MVME136 board. |
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| 4 | * The tick frequency is 1 millisecond. |
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| 5 | * |
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| 6 | * Input parameters: NONE |
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| 7 | * |
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| 8 | * Output parameters: NONE |
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| 9 | * |
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| 10 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 11 | * On-Line Applications Research Corporation (OAR). |
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| 12 | * All rights assigned to U.S. Government, 1994. |
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| 13 | * |
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| 14 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 15 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 16 | * notice must appear in all copies of this file and its derivatives. |
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| 17 | * |
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| 18 | * $Id$ |
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| 19 | */ |
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| 20 | |
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| 21 | #include <stdlib.h> |
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| 22 | |
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| 23 | #include <rtems.h> |
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| 24 | #include <bsp.h> |
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| 25 | #include <clockdrv.h> |
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| 26 | |
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| 27 | rtems_unsigned32 Clock_isrs; /* ISRs until next tick */ |
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| 28 | volatile rtems_unsigned32 Clock_driver_ticks; |
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| 29 | /* ticks since initialization */ |
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| 30 | rtems_isr_entry Old_ticker; |
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| 31 | |
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| 32 | rtems_device_driver Clock_initialize( |
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| 33 | rtems_device_major_number major, |
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| 34 | rtems_device_minor_number minor, |
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| 35 | void *pargp, |
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| 36 | rtems_id tid, |
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| 37 | rtems_unsigned32 *rval |
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| 38 | ) |
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| 39 | { |
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| 40 | Install_clock( Clock_isr ); |
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| 41 | } |
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| 42 | |
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| 43 | void ReInstall_clock( |
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| 44 | rtems_isr_entry clock_isr |
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| 45 | ) |
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| 46 | { |
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| 47 | rtems_unsigned32 isrlevel = 0 ; |
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| 48 | |
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| 49 | rtems_interrupt_disable( isrlevel ); |
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| 50 | (void) set_vector( clock_isr, TIMER_VECTOR, 1 ); |
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| 51 | rtems_interrupt_enable( isrlevel ); |
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| 52 | } |
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| 53 | |
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| 54 | void Install_clock( |
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| 55 | rtems_isr_entry clock_isr |
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| 56 | ) |
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| 57 | { |
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| 58 | rtems_unsigned8 data; |
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| 59 | |
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| 60 | Clock_driver_ticks = 0; |
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| 61 | Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; |
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| 62 | |
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| 63 | if ( BSP_Configuration.ticks_per_timeslice ) { |
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| 64 | Old_ticker = (rtems_isr_entry) set_vector( clock_isr, TIMER_VECTOR, 1 ); |
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| 65 | |
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| 66 | Z8x36_WRITE( TIMER, MASTER_CFG, 0xd4 ); |
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| 67 | Z8x36_READ ( TIMER, MASTER_INTR, data ); |
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| 68 | Z8x36_WRITE( TIMER, MASTER_INTR, (data & 0x7E) ); |
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| 69 | Z8x36_WRITE( TIMER, CT1_TIME_CONST_MSB, 0x04 ); |
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| 70 | Z8x36_WRITE( TIMER, CT1_TIME_CONST_LSB, 0xCE ); |
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| 71 | Z8x36_WRITE( TIMER, CT1_MODE_SPEC, 0x83 ); |
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| 72 | Z8x36_WRITE( TIMER, CNT_TMR_VECTOR, TIMER_VECTOR ); |
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| 73 | Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0x20 ); |
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| 74 | Z8x36_READ ( TIMER, MASTER_INTR, data ); |
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| 75 | Z8x36_WRITE( TIMER, MASTER_INTR, (data & 0xDA) | 0x80 ); |
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| 76 | |
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| 77 | /* |
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| 78 | * ACC_IC54 - interrupt 5 will be vectored and mapped to level 6 |
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| 79 | */ |
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| 80 | |
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| 81 | data = (*(rtems_unsigned8 *)0x0D00000B); |
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| 82 | (*(rtems_unsigned8 *)0x0D00000B) = (data & 0x7F) | 0x60; |
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| 83 | |
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| 84 | Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0xC6 ); |
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| 85 | |
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| 86 | atexit( Clock_exit ); |
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| 87 | } |
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| 88 | } |
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| 89 | |
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| 90 | void Clock_exit( void ) |
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| 91 | { |
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| 92 | rtems_unsigned8 data; |
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| 93 | |
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| 94 | if ( BSP_Configuration.ticks_per_timeslice ) { |
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| 95 | |
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| 96 | Z8x36_READ ( TIMER, MASTER_INTR, data ); |
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| 97 | Z8x36_WRITE( TIMER, MASTER_INTR, (data & 0x01) ); |
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| 98 | /* do not restore old vector */ |
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| 99 | |
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| 100 | } |
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| 101 | } |
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