1 | /* |
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2 | * CSB360 hardware startup routines |
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3 | * |
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4 | * This is where the real hardware setup is done. A minimal stack |
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5 | * has been provided by the start.S code. No normal C or RTEMS |
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6 | * functions can be called from here. |
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7 | * |
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8 | * This initialization code based on hardware settings of dBUG |
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9 | * monitor. This must be changed if you like to run it immediately |
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10 | * after reset. |
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11 | * |
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12 | * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia |
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13 | * Author: Victor V. Vengerov <vvv@oktet.ru> |
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14 | * |
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15 | * Based on work: |
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16 | * Author: |
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17 | * David Fiddes, D.J@fiddes.surfaid.org |
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18 | * http://www.calm.hw.ac.uk/davidf/coldfire/ |
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19 | * |
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20 | * COPYRIGHT (c) 1989-1998. |
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21 | * On-Line Applications Research Corporation (OAR). |
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22 | * |
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23 | * The license and distribution terms for this file may be |
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24 | * found in the file LICENSE in this distribution or at |
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25 | * |
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26 | * http://www.rtems.com/license/LICENSE. |
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27 | * |
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28 | * $Id$ |
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29 | */ |
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30 | |
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31 | #include <rtems.h> |
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32 | #include <bsp.h> |
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33 | #include <mcf5272/mcf5272.h> |
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34 | |
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35 | /* Set the pointers to the modules */ |
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36 | sim_regs_t *g_sim_regs = (void *) MCF5272_SIM_BASE(BSP_MBAR); |
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37 | intctrl_regs_t *g_intctrl_regs = (void *) MCF5272_INT_BASE(BSP_MBAR); |
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38 | chipsel_regs_t *g_chipsel_regs = (void *) MCF5272_CS_BASE(BSP_MBAR); |
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39 | gpio_regs_t *g_gpio_regs = (void *) MCF5272_GPIO_BASE(BSP_MBAR); |
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40 | qspi_regs_t *g_qspi_regs = (void *) MCF5272_QSPI_BASE(BSP_MBAR); |
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41 | pwm_regs_t *g_pwm_regs = (void *) MCF5272_PWM_BASE(BSP_MBAR); |
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42 | dma_regs_t *g_dma_regs = (void *) MCF5272_DMAC_BASE(BSP_MBAR); |
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43 | uart_regs_t *g_uart0_regs = (void *) MCF5272_UART0_BASE(BSP_MBAR); |
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44 | uart_regs_t *g_uart1_regs = (void *) MCF5272_UART1_BASE(BSP_MBAR); |
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45 | timer_regs_t *g_timer_regs = (void *) MCF5272_TIMER_BASE(BSP_MBAR); |
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46 | plic_regs_t *g_plic_regs = (void *) MCF5272_PLIC_BASE(BSP_MBAR); |
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47 | enet_regs_t *g_enet_regs = (void *) MCF5272_ENET_BASE(BSP_MBAR); |
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48 | usb_regs_t *g_usb_regs = (void *) MCF5272_USB_BASE(BSP_MBAR); |
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49 | |
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50 | #define m68k_set_cacr( _cacr ) \ |
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51 | asm volatile ( "movec %0,%%cacr\n\t" \ |
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52 | "nop\n" \ |
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53 | : : "d" (_cacr) ) |
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54 | |
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55 | #define m68k_set_acr0( _acr0 ) \ |
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56 | asm volatile ( "movec %0,%%acr0\n\t" \ |
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57 | "nop\n\t" \ |
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58 | : : "d" (_acr0) ) |
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59 | |
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60 | #define m68k_set_acr1( _acr1 ) \ |
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61 | asm volatile ( "movec %0,%%acr1\n\t" \ |
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62 | "nop\n\t" \ |
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63 | : : "d" (_acr1) ) |
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64 | |
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65 | #define m68k_set_srambar( _rambar0 ) \ |
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66 | asm volatile ( "movec %0,%%rambar0\n\t" \ |
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67 | "nop\n\t" \ |
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68 | : : "d" (_rambar0) ) |
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69 | |
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70 | #define m68k_set_mbar( _mbar ) \ |
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71 | asm volatile ( "movec %0,%%mbar\n\t" \ |
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72 | "nop\n\t" \ |
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73 | : : "d" (_mbar) ) |
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74 | |
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75 | #define mcf5272_enable_cache() \ |
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76 | m68k_set_cacr( MCF5272_CACR_CENB ) |
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77 | |
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78 | |
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79 | #define mcf5272_disable_cache() \ |
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80 | asm volatile ( "nop\n\t" \ |
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81 | "movec %0,%%cacr\n\t" \ |
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82 | "nop\n\t" \ |
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83 | "movec %0,%%cacr\n\t" \ |
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84 | "nop\n\t" \ |
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85 | : : "d" (MCF5272_CACR_CINV) ) |
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86 | |
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87 | /* init5272 -- |
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88 | * Initialize MCF5272 on-chip modules |
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89 | * |
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90 | * PARAMETERS: |
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91 | * none |
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92 | * |
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93 | * RETURNS: |
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94 | * none |
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95 | */ |
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96 | void |
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97 | init5272(void) |
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98 | { |
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99 | extern void clear_bss(void); |
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100 | extern void start_csb360(void); |
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101 | |
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102 | /* Invalidate the cache - WARNING: It won't complete for 64 clocks */ |
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103 | m68k_set_cacr(MCF5272_CACR_CINV); |
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104 | |
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105 | /* Set Module Base Address register */ |
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106 | m68k_set_mbar((BSP_MBAR & MCF5272_MBAR_BA) | MCF5272_MBAR_V); |
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107 | |
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108 | /* Set RAM Base Address register */ |
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109 | m68k_set_srambar((BSP_RAMBAR & MCF5272_RAMBAR_BA) | MCF5272_RAMBAR_V); |
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110 | |
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111 | /* Set System Control Register: |
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112 | * Enet has highest priority, 16384 bus cycles before timeout |
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113 | */ |
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114 | g_sim_regs->scr = (MCF5272_SCR_HWR_16384); |
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115 | |
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116 | /* System Protection Register: |
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117 | * Enable Hardware watchdog timer. |
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118 | */ |
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119 | g_sim_regs->spr = MCF5272_SPR_HWTEN; |
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120 | |
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121 | /* Clear and mask all interrupts */ |
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122 | g_intctrl_regs->icr1 = 0x88888888; |
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123 | g_intctrl_regs->icr2 = 0x88888888; |
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124 | g_intctrl_regs->icr3 = 0x88888888; |
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125 | g_intctrl_regs->icr4 = 0x88880000; |
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126 | |
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127 | /* Copy the interrupt vector table to SRAM */ |
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128 | { |
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129 | extern void INTERRUPT_VECTOR(void); |
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130 | uint32_t *inttab = (uint32_t *)&INTERRUPT_VECTOR; |
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131 | uint32_t *intvec = (uint32_t *)BSP_RAMBAR; |
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132 | register int i; |
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133 | for (i = 0; i < 256; i++) |
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134 | { |
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135 | *(intvec++) = *(inttab++); |
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136 | } |
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137 | } |
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138 | m68k_set_vbr(BSP_RAMBAR); |
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139 | |
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140 | |
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141 | /* |
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142 | * Setup ACRs so that if cache turned on, periphal accesses |
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143 | * are not messed up. (Non-cacheable, serialized) |
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144 | */ |
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145 | |
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146 | m68k_set_acr0(MCF5272_ACR_BASE(BSP_MEM_ADDR_SDRAM) | |
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147 | MCF5272_ACR_MASK(BSP_MEM_MASK_SDRAM) | |
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148 | MCF5272_ACR_EN | |
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149 | MCF5272_ACR_SM_ANY); |
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150 | |
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151 | /* |
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152 | m68k_set_acr1 (MCF5206E_ACR_BASE(BSP_MEM_ADDR_FLASH) | |
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153 | MCF5206E_ACR_MASK(BSP_MEM_MASK_FLASH) | |
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154 | MCF5206E_ACR_EN | |
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155 | MCF5206E_ACR_SM_ANY); |
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156 | */ |
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157 | |
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158 | /* Enable the caches */ |
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159 | m68k_set_cacr(MCF5272_CACR_CENB | |
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160 | MCF5272_CACR_DCM); /* Default is not cached */ |
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161 | |
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162 | /* |
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163 | * Copy data, clear BSS, switch stacks and call boot_card() |
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164 | */ |
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165 | /* |
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166 | CopyDataClearBSSAndStart(BSP_MEM_SIZE_ESRAM - 0x400); |
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167 | */ |
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168 | clear_bss(); |
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169 | start_csb360(); |
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170 | |
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171 | } |
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