source: rtems/c/src/lib/libbsp/m68k/csb360/startup/init5272.c @ a840853

4.104.114.95
Last change on this file since a840853 was a840853, checked in by Ralf Corsepius <ralf.corsepius@…>, on 08/19/08 at 11:25:05

Add missing prototypes.

  • Property mode set to 100644
File size: 5.2 KB
Line 
1/*
2 *  CSB360 hardware startup routines
3 *
4 *  This is where the real hardware setup is done. A minimal stack
5 *  has been provided by the start.S code. No normal C or RTEMS
6 *  functions can be called from here.
7 *
8 *  This initialization code based on hardware settings of dBUG
9 *  monitor. This must be changed if you like to run it immediately
10 *  after reset.
11 *
12 *  Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
13 *  Author: Victor V. Vengerov <vvv@oktet.ru>
14 *
15 *  Based on work:
16 *  Author:
17 *    David Fiddes, D.J@fiddes.surfaid.org
18 *    http://www.calm.hw.ac.uk/davidf/coldfire/
19 *
20 *  COPYRIGHT (c) 1989-1998.
21 *  On-Line Applications Research Corporation (OAR).
22 *
23 *  The license and distribution terms for this file may be
24 *  found in the file LICENSE in this distribution or at
25 *
26 *  http://www.rtems.com/license/LICENSE.
27 *
28 *  $Id$
29 */
30
31#include <rtems.h>
32#include <bsp.h>
33#include <mcf5272/mcf5272.h>
34
35/* Set the pointers to the modules */
36sim_regs_t *g_sim_regs            = (void *) MCF5272_SIM_BASE(BSP_MBAR);
37intctrl_regs_t *g_intctrl_regs    = (void *) MCF5272_INT_BASE(BSP_MBAR);
38chipsel_regs_t *g_chipsel_regs    = (void *) MCF5272_CS_BASE(BSP_MBAR);
39gpio_regs_t *g_gpio_regs          = (void *) MCF5272_GPIO_BASE(BSP_MBAR);
40qspi_regs_t *g_qspi_regs          = (void *) MCF5272_QSPI_BASE(BSP_MBAR);
41pwm_regs_t *g_pwm_regs            = (void *) MCF5272_PWM_BASE(BSP_MBAR);
42dma_regs_t *g_dma_regs            = (void *) MCF5272_DMAC_BASE(BSP_MBAR);
43uart_regs_t *g_uart0_regs         = (void *) MCF5272_UART0_BASE(BSP_MBAR);
44uart_regs_t *g_uart1_regs         = (void *) MCF5272_UART1_BASE(BSP_MBAR);
45timer_regs_t *g_timer_regs        = (void *) MCF5272_TIMER_BASE(BSP_MBAR);
46plic_regs_t *g_plic_regs          = (void *) MCF5272_PLIC_BASE(BSP_MBAR);
47enet_regs_t *g_enet_regs          = (void *) MCF5272_ENET_BASE(BSP_MBAR);
48usb_regs_t *g_usb_regs            = (void *) MCF5272_USB_BASE(BSP_MBAR);
49
50#define m68k_set_cacr( _cacr ) \
51  asm volatile ( "movec %0,%%cacr\n\t" \
52                 "nop\n" \
53                 : : "d" (_cacr) )
54
55#define m68k_set_acr0( _acr0 ) \
56  asm volatile (  "movec %0,%%acr0\n\t" \
57                  "nop\n\t" \
58                  : : "d" (_acr0) )
59
60#define m68k_set_acr1( _acr1 ) \
61  asm volatile (  "movec %0,%%acr1\n\t" \
62                  "nop\n\t" \
63                  : : "d" (_acr1) )
64
65#define m68k_set_srambar( _rambar0 ) \
66  asm volatile (  "movec %0,%%rambar0\n\t" \
67                  "nop\n\t" \
68                  : : "d" (_rambar0) )
69
70#define m68k_set_mbar( _mbar ) \
71  asm volatile (  "movec %0,%%mbar\n\t" \
72                  "nop\n\t" \
73                  : : "d" (_mbar) )
74
75#define mcf5272_enable_cache() \
76  m68k_set_cacr( MCF5272_CACR_CENB )
77
78
79#define mcf5272_disable_cache() \
80  asm volatile (  "nop\n\t"    \
81                  "movec %0,%%cacr\n\t" \
82                  "nop\n\t" \
83                  "movec %0,%%cacr\n\t" \
84                  "nop\n\t" \
85                  : : "d" (MCF5272_CACR_CINV) )
86
87/* init5272 --
88 *     Initialize MCF5272 on-chip modules
89 *
90 * PARAMETERS:
91 *     none
92 *
93 * RETURNS:
94 *     none
95 */
96void
97init5272(void)
98{
99    extern void clear_bss(void);
100    extern void start_csb360(void);
101
102    /* Invalidate the cache - WARNING: It won't complete for 64 clocks */
103    m68k_set_cacr(MCF5272_CACR_CINV);
104
105    /* Set Module Base Address register */
106    m68k_set_mbar((BSP_MBAR & MCF5272_MBAR_BA) | MCF5272_MBAR_V);
107
108    /* Set RAM Base Address register */
109    m68k_set_srambar((BSP_RAMBAR & MCF5272_RAMBAR_BA) | MCF5272_RAMBAR_V);
110   
111    /* Set System Control Register:
112     * Enet has highest priority, 16384 bus cycles before timeout
113     */
114    g_sim_regs->scr = (MCF5272_SCR_HWR_16384);
115   
116    /* System Protection Register:
117     * Enable Hardware watchdog timer.
118     */
119    g_sim_regs->spr = MCF5272_SPR_HWTEN;
120
121    /* Clear and mask all interrupts */
122    g_intctrl_regs->icr1 = 0x88888888;
123    g_intctrl_regs->icr2 = 0x88888888;
124    g_intctrl_regs->icr3 = 0x88888888;
125    g_intctrl_regs->icr4 = 0x88880000;
126
127    /* Copy the interrupt vector table to SRAM */
128    {
129        extern void INTERRUPT_VECTOR(void);
130        uint32_t *inttab = (uint32_t *)&INTERRUPT_VECTOR;
131        uint32_t *intvec = (uint32_t *)BSP_RAMBAR;
132        register int i;
133        for (i = 0; i < 256; i++)
134        {
135            *(intvec++) = *(inttab++);
136        }
137    }
138    m68k_set_vbr(BSP_RAMBAR);
139   
140   
141    /*
142     * Setup ACRs so that if cache turned on, periphal accesses
143     * are not messed up.  (Non-cacheable, serialized)
144     */
145
146    m68k_set_acr0(MCF5272_ACR_BASE(BSP_MEM_ADDR_SDRAM)    |
147                  MCF5272_ACR_MASK(BSP_MEM_MASK_SDRAM)    |
148                  MCF5272_ACR_EN                          |
149                  MCF5272_ACR_SM_ANY);
150
151/*
152    m68k_set_acr1 (MCF5206E_ACR_BASE(BSP_MEM_ADDR_FLASH) |
153                   MCF5206E_ACR_MASK(BSP_MEM_MASK_FLASH) |
154                   MCF5206E_ACR_EN                       |
155                   MCF5206E_ACR_SM_ANY);
156*/
157
158    /* Enable the caches */
159    m68k_set_cacr(MCF5272_CACR_CENB |
160                  MCF5272_CACR_DCM);       /* Default is not cached */
161 
162  /*
163   * Copy data, clear BSS, switch stacks and call boot_card()
164   */
165/*
166  CopyDataClearBSSAndStart(BSP_MEM_SIZE_ESRAM - 0x400);
167*/
168    clear_bss();
169    start_csb360();
170
171}
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