source: rtems/c/src/lib/libbsp/m68k/csb360/startup/init5272.c @ 02e708d

4.104.114.84.95
Last change on this file since 02e708d was 02e708d, checked in by Jay Monkman <jtm@…>, on Aug 3, 2004 at 5:01:51 AM

2004-08-03 Jay Monkman <jtm@…>

  • .cvsignore, ChangeLog?, Makefile.am, README, bsp_specs, configure.ac, times, console/.cvsignore, console/console-io.c, include/.cvsignore, include/bsp.h, include/coverhd.h, include/tm27.h, network/network.c, start/.cvsignore, start/start.S, startup/.cvsignore, startup/bspclean.c, startup/bspstart.c, startup/init5272.c, startup/linkcmds: New files.
  • Property mode set to 100644
File size: 5.3 KB
Line 
1/*
2 *  CSB360 hardware startup routines
3 *
4 *  This is where the real hardware setup is done. A minimal stack
5 *  has been provided by the start.S code. No normal C or RTEMS
6 *  functions can be called from here.
7 *
8 *  This initialization code based on hardware settings of dBUG
9 *  monitor. This must be changed if you like to run it immediately
10 *  after reset.
11 *
12 *  Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
13 *  Author: Victor V. Vengerov <vvv@oktet.ru>
14 *
15 *  Based on work:
16 *  Author:
17 *    David Fiddes, D.J@fiddes.surfaid.org
18 *    http://www.calm.hw.ac.uk/davidf/coldfire/
19 *
20 *  COPYRIGHT (c) 1989-1998.
21 *  On-Line Applications Research Corporation (OAR).
22 *  Copyright assigned to U.S. Government, 1994.
23 *
24 *  The license and distribution terms for this file may be
25 *  found in the file LICENSE in this distribution or at
26 *
27 *  http://www.OARcorp.com/rtems/license.html.
28 *
29 *  init5206e.c,v 1.1 2001/10/26 19:30:11 joel Exp
30 */
31
32#include <rtems.h>
33#include <bsp.h>
34#include <mcf5272/mcf5272.h>
35
36/* Set the pointers to the modules */
37sim_regs_t *g_sim_regs            = (void *) MCF5272_SIM_BASE(BSP_MBAR);
38intctrl_regs_t *g_intctrl_regs    = (void *) MCF5272_INT_BASE(BSP_MBAR);
39chipsel_regs_t *g_chipsel_regs    = (void *) MCF5272_CS_BASE(BSP_MBAR);
40gpio_regs_t *g_gpio_regs          = (void *) MCF5272_GPIO_BASE(BSP_MBAR);
41qspi_regs_t *g_qspi_regs          = (void *) MCF5272_QSPI_BASE(BSP_MBAR);
42pwm_regs_t *g_pwm_regs            = (void *) MCF5272_PWM_BASE(BSP_MBAR);
43dma_regs_t *g_dma_regs            = (void *) MCF5272_DMAC_BASE(BSP_MBAR);
44uart_regs_t *g_uart0_regs         = (void *) MCF5272_UART0_BASE(BSP_MBAR);
45uart_regs_t *g_uart1_regs         = (void *) MCF5272_UART1_BASE(BSP_MBAR);
46timer_regs_t *g_timer_regs        = (void *) MCF5272_TIMER_BASE(BSP_MBAR);
47plic_regs_t *g_plic_regs          = (void *) MCF5272_PLIC_BASE(BSP_MBAR);
48enet_regs_t *g_enet_regs          = (void *) MCF5272_ENET_BASE(BSP_MBAR);
49usb_regs_t *g_usb_regs            = (void *) MCF5272_USB_BASE(BSP_MBAR);
50
51#define m68k_set_cacr( _cacr ) \
52  asm volatile ( "movec %0,%%cacr\n\t" \
53                 "nop\n" \
54                 : : "d" (_cacr) )
55
56#define m68k_set_acr0( _acr0 ) \
57  asm volatile (  "movec %0,%%acr0\n\t" \
58                  "nop\n\t" \
59                  : : "d" (_acr0) )
60
61#define m68k_set_acr1( _acr1 ) \
62  asm volatile (  "movec %0,%%acr1\n\t" \
63                  "nop\n\t" \
64                  : : "d" (_acr1) )
65
66#define m68k_set_srambar( _rambar0 ) \
67  asm volatile (  "movec %0,%%rambar0\n\t" \
68                  "nop\n\t" \
69                  : : "d" (_rambar0) )
70
71#define m68k_set_mbar( _mbar ) \
72  asm volatile (  "movec %0,%%mbar\n\t" \
73                  "nop\n\t" \
74                  : : "d" (_mbar) )
75
76#define mcf5272_enable_cache() \
77  m68k_set_cacr( MCF5272_CACR_CENB )
78
79
80#define mcf5272_disable_cache() \
81  asm volatile (  "nop\n\t"    \
82                  "movec %0,%%cacr\n\t" \
83                  "nop\n\t" \
84                  "movec %0,%%cacr\n\t" \
85                  "nop\n\t" \
86                  : : "d" (MCF5272_CACR_CINV) )
87
88/* init5272 --
89 *     Initialize MCF5272 on-chip modules
90 *
91 * PARAMETERS:
92 *     none
93 *
94 * RETURNS:
95 *     none
96 */
97void
98init5272(void)
99{
100    extern void clear_bss(void);
101    extern void start_csb360(void);
102    int i;
103
104    /* Invalidate the cache - WARNING: It won't complete for 64 clocks */
105    m68k_set_cacr(MCF5272_CACR_CINV);
106
107    /* Set Module Base Address register */
108    m68k_set_mbar((BSP_MBAR & MCF5272_MBAR_BA) | MCF5272_MBAR_V);
109
110    /* Set RAM Base Address register */
111    m68k_set_srambar((BSP_RAMBAR & MCF5272_RAMBAR_BA) | MCF5272_RAMBAR_V);
112   
113    /* Set System Control Register:
114     * Enet has highest priority, 16384 bus cycles before timeout
115     */
116    g_sim_regs->scr = (MCF5272_SCR_HWR_16384);
117   
118    /* System Protection Register:
119     * Enable Hardware watchdog timer.
120     */
121    g_sim_regs->spr = MCF5272_SPR_HWTEN;
122
123    /* Clear and mask all interrupts */
124    g_intctrl_regs->icr1 = 0x88888888;
125    g_intctrl_regs->icr2 = 0x88888888;
126    g_intctrl_regs->icr3 = 0x88888888;
127    g_intctrl_regs->icr4 = 0x88880000;
128
129    /* Copy the interrupt vector table to SRAM */
130    {
131        extern void INTERRUPT_VECTOR();
132        rtems_unsigned32 *inttab = (rtems_unsigned32 *)&INTERRUPT_VECTOR;
133        rtems_unsigned32 *intvec = (rtems_unsigned32 *)BSP_RAMBAR;
134        register int i;
135        for (i = 0; i < 256; i++)
136        {
137            *(intvec++) = *(inttab++);
138        }
139    }
140    m68k_set_vbr(BSP_RAMBAR);
141   
142   
143    /*
144     * Setup ACRs so that if cache turned on, periphal accesses
145     * are not messed up.  (Non-cacheable, serialized)
146     */
147
148    m68k_set_acr0(MCF5272_ACR_BASE(BSP_MEM_ADDR_SDRAM)    |
149                  MCF5272_ACR_MASK(BSP_MEM_MASK_SDRAM)    |
150                  MCF5272_ACR_EN                          |
151                  MCF5272_ACR_SM_ANY);
152
153/*
154    m68k_set_acr1 (MCF5206E_ACR_BASE(BSP_MEM_ADDR_FLASH) |
155                   MCF5206E_ACR_MASK(BSP_MEM_MASK_FLASH) |
156                   MCF5206E_ACR_EN                       |
157                   MCF5206E_ACR_SM_ANY);
158*/
159
160    /* Enable the caches */
161    m68k_set_cacr(MCF5272_CACR_CENB |
162                  MCF5272_CACR_DCM);       /* Default is not cached */
163 
164  /*
165   * Copy data, clear BSS, switch stacks and call boot_card()
166   */
167/*
168  CopyDataClearBSSAndStart(BSP_MEM_SIZE_ESRAM - 0x400);
169*/
170    clear_bss();
171    start_csb360();
172
173}
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