source: rtems/c/src/lib/libbsp/m68k/csb360/include/bsp.h @ 7c70c1d7

4.115
Last change on this file since 7c70c1d7 was 7c70c1d7, checked in by Toma Radu <radustoma@…>, on 12/30/13 at 17:08:13

m68k_csb360: doxygen improvement

Add doxygen to the header files in the m68k/cdb360 directory.

  • Property mode set to 100644
File size: 4.4 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup m68k_csb360
5 *
6 * @brief Global BSP definitions.
7 */
8
9/*
10 * Board Support Package for CSB360 evaluation board
11 * BSP definitions
12 *
13 * Copyright 2004 Cogent Computer Systems
14 * Author: Jay Monkman <jtm@lopingdog.com>
15 *
16 * Derived from mcf5206elite BSP:
17 * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
18 * Author: Victor V. Vengerov <vvv@oktet.ru>
19 *
20 * The license and distribution terms for this file may be
21 * found in the file LICENSE in this distribution or at
22 *
23 * http://www.rtems.com/license/LICENSE.
24 */
25
26#ifndef _BSP_H
27#define _BSP_H
28
29#include <mcf5272/mcf5272.h>
30
31/**
32 * @defgroup m68k_csb360 CSB360 Support
33 *
34 * @ingroup bsp_m68k
35 *
36 * @brief CSB360 support.
37 */
38
39
40/*** Board resources allocation ***/
41#define BSP_MEM_ADDR_SRAM 0x20000000
42#define BSP_MEM_SIZE_SRAM 4096
43
44/* Location and size of sdram. Note this includes space used by
45 * umon.
46 */
47#define BSP_MEM_ADDR_SDRAM 0x00000000
48#define BSP_MEM_MASK_SDRAM 0x01ffffff
49#define BSP_MEM_SIZE_SDRAM (32 * 1024 * 1024)
50
51/* Address to put SIM Modules */
52#define BSP_MBAR 0x10000000
53
54/* Address to put SRAM */
55#define BSP_RAMBAR BSP_MEM_ADDR_SRAM
56
57/* Interrupt Vectors */
58#define BSP_INTVEC_INT1   65
59#define BSP_INTVEC_INT2   66
60#define BSP_INTVEC_INT3   67
61#define BSP_INTVEC_INT4   68
62#define BSP_INTVEC_TMR0   69
63#define BSP_INTVEC_TMR1   70
64#define BSP_INTVEC_TMR2   71
65#define BSP_INTVEC_TMR3   72
66#define BSP_INTVEC_UART1  73
67#define BSP_INTVEC_UART2  74
68#define BSP_INTVEC_PLIP   75
69#define BSP_INTVEC_PLIA   76
70#define BSP_INTVEC_USB0   77
71#define BSP_INTVEC_USB1   78
72#define BSP_INTVEC_USB2   79
73#define BSP_INTVEC_USB3   80
74#define BSP_INTVEC_USB4   81
75#define BSP_INTVEC_USB5   82
76#define BSP_INTVEC_USB6   83
77#define BSP_INTVEC_USB7   84
78#define BSP_INTVEC_DMA    85
79#define BSP_INTVEC_ERX    86
80#define BSP_INTVEC_ETX    87
81#define BSP_INTVEC_ENTC   88
82#define BSP_INTVEC_QSPI   89
83#define BSP_INTVEC_INT5   90
84#define BSP_INTVEC_INT6   91
85#define BSP_INTVEC_SWTO   92
86
87#define BSP_INTLVL_INT1   1
88#define BSP_INTLVL_INT2   1
89#define BSP_INTLVL_INT3   1
90#define BSP_INTLVL_INT4   1
91#define BSP_INTLVL_TMR0   1
92#define BSP_INTLVL_TMR1   1
93#define BSP_INTLVL_TMR2   1
94#define BSP_INTLVL_TMR3   1
95#define BSP_INTLVL_UART1  1
96#define BSP_INTLVL_UART2  1
97#define BSP_INTLVL_PLIP   1
98#define BSP_INTLVL_PLIA   1
99#define BSP_INTLVL_USB0   1
100#define BSP_INTLVL_USB1   1
101#define BSP_INTLVL_USB2   1
102#define BSP_INTLVL_USB3   1
103#define BSP_INTLVL_USB4   1
104#define BSP_INTLVL_USB5   1
105#define BSP_INTLVL_USB6   1
106#define BSP_INTLVL_USB7   1
107#define BSP_INTLVL_DMA    1
108#define BSP_INTLVL_ERX    1
109#define BSP_INTLVL_ETX    1
110#define BSP_INTLVL_ENTC   1
111#define BSP_INTLVL_QSPI   1
112#define BSP_INTLVL_INT5   1
113#define BSP_INTLVL_INT6   1
114#define BSP_INTLVL_SWTO   1
115
116
117
118#ifndef ASM
119
120#ifdef __cplusplus
121extern "C" {
122#endif
123
124#include <bspopts.h>
125#include <rtems.h>
126#include <rtems/console.h>
127#include <rtems/iosupp.h>
128#include <rtems/clockdrv.h>
129#include <bsp/default-initial-extension.h>
130
131struct rtems_bsdnet_ifconfig;
132extern int rtems_enet_driver_attach (struct rtems_bsdnet_ifconfig *config);
133#define RTEMS_BSP_NETWORK_DRIVER_NAME   "eth0"
134#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_enet_driver_attach
135
136/* System frequency */
137#define BSP_SYSTEM_FREQUENCY (66 * 1000 * 1000)
138
139/*
140 *  Simple spin delay in microsecond units for device drivers.
141 *  This is very dependent on the clock speed of the target.
142 */
143
144#define delay( microseconds ) \
145  { register uint32_t _delay=(microseconds); \
146    register uint32_t _tmp=123; \
147    __asm__ volatile( "0: \
148                     nbcd      %0 ; \
149                     nbcd      %0 ; \
150                     dbf       %1,0b" \
151                  : "=d" (_tmp), "=d" (_delay) \
152                  : "0"  (_tmp), "1"  (_delay) ); \
153  }
154
155/*
156 * Real-Time Clock Driver Table Entry
157 * NOTE: put this entry to the device driver table AFTER I2C bus driver!
158 */
159#define RTC_DRIVER_TABLE_ENTRY \
160    { rtc_initialize, NULL, NULL, NULL, NULL, NULL }
161extern rtems_device_driver rtc_initialize(
162    rtems_device_major_number major,
163    rtems_device_minor_number minor,
164    void *arg
165);
166
167/* miscellaneous stuff assumed to exist */
168
169extern rtems_isr_entry M68Kvec[];   /* vector table address */
170
171extern rtems_isr (*rtems_clock_hook)(rtems_vector_number);
172
173/* functions */
174
175rtems_isr_entry set_vector(
176  rtems_isr_entry     handler,
177  rtems_vector_number vector,
178  int                 type
179);
180
181#ifdef __cplusplus
182}
183#endif
184
185#endif /* ASM */
186
187#endif
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