source: rtems/c/src/lib/libbsp/m68k/av5282/startup/init5282.c @ 6ea100c1

4.104.114.9
Last change on this file since 6ea100c1 was 0b1cb769, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 11, 2006 at 9:43:36 PM

2006-09-11 Joel Sherrill <joel@…>

  • startup/init5282.c: Convert C++ style comments to C style.
  • Property mode set to 100644
File size: 2.3 KB
Line 
1/*
2 *  This is where the real hardware setup is done. A minimal stack
3 *  has been provided by the start.S code. No normal C or RTEMS
4 *  functions can be called from here.
5 *
6 * This routine is pretty simple for the uC5282 because all the hard
7 * work has been done by the bootstrap dBUG code.
8 */
9
10#include <rtems.h>
11#include <bsp.h>
12#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
13#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
14#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
15#define MM_SDRAM_BASE           (0x00000000)
16
17void Init5282 (void)
18{
19    extern void CopyDataClearBSSAndStart (void);
20    int x;
21    int temp = 0;
22   
23    /*Setup the GPIO Registers */
24    MCF5282_GPIO_PBCDPAR = 0x80;
25    MCF5282_GPIO_PEPAR = 0x5100;
26    MCF5282_GPIO_PJPAR = 0xFF;
27    MCF5282_GPIO_PASPAR =  0x0000;
28    MCF5282_GPIO_PEHLPAR = 0xC0;
29    MCF5282_GPIO_PUAPAR = 0x0F;
30    MCF5282_QADC_DDRQB = 0x07;
31    MCF5282_GPTA_GPTDDR = 0x0C;
32    MCF5282_GPTA_GPTPORT = 0x4;
33   
34    /*Setup the Chip Selects so CS0 is flash */
35    MCF5282_CS0_CSAR =(0xff800000 & 0xffff0000)>>16;
36    MCF5282_CS0_CSMR = 0x007f0001;
37    MCF5282_CS0_CSCR =(((0xf)&0x0F)<<10)|(1<<8)|(0x80);
38
39        /*Setup the SDRAM  */
40        for(x=0; x<20000; x++)
41        {
42                temp +=1;
43        }
44        MCF5282_SDRAMC_DCR  = 0x00000239;
45        MCF5282_SDRAMC_DACR0 = 0x00001320;
46        MCF5282_SDRAMC_DMR0 = (0x00FC0000) | (0x00000001);
47        for(x=0; x<20000; x++)
48        {
49                temp +=1;
50        }
51        /* set ip ( bit 3 ) in dacr */
52        MCF5282_SDRAMC_DACR0 |= (0x00000008) ; 
53        /* init precharge */
54        *((short *)MM_SDRAM_BASE) = 0;
55        /* set RE in dacr */
56        MCF5282_SDRAMC_DACR0 |= (0x00008000); 
57        /* wait */
58        for(x=0; x<20000; x++)
59        {
60                temp +=1;
61        }
62        /* issue IMRS */
63        MCF5282_SDRAMC_DACR0 |= (0x00000040);
64        *((short *)MM_SDRAM_BASE) = 0x0000;
65        for(x=0; x<60000; x++)
66        {
67                temp +=1;
68        }
69        *((unsigned long*)MM_SDRAM_BASE)=0x12345678;
70   
71    /* Copy the interrupt vector table to address 0x0 in SDRAM */
72    {
73        extern void INTERRUPT_VECTOR();
74        uint32_t *inttab = (uint32_t *)&INTERRUPT_VECTOR;
75        uint32_t *intvec = (uint32_t *)0x0;
76        register int i;
77        for (i = 0; i < 256; i++)
78        {
79            *(intvec++) = *(inttab++);
80        }
81    }
82        /*
83     * Copy data, clear BSS and call boot_card()
84     */
85    CopyDataClearBSSAndStart ();
86}
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