source: rtems/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c @ f1c53e8e

4.104.114.95
Last change on this file since f1c53e8e was cafa2c5, checked in by Joel Sherrill <joel.sherrill@…>, on 12/04/07 at 22:22:03

2007-12-04 Joel Sherrill <joel.sherrill@…>

  • startup/bspstart.c: Move interrupt_stack_size field from CPU Table to Configuration Table. Eliminate CPU Table from all ports. Delete references to CPU Table in all forms.
  • Property mode set to 100644
File size: 5.4 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *
16 *  The license and distribution terms for this file may be
17 *  found in the file LICENSE in this distribution or at
18 *
19 *  http://www.rtems.com/license/LICENSE.
20 *
21 *  $Id$
22 */
23
24#include <bsp.h>
25#include <rtems/libio.h>
26#include <rtems/libcsupport.h>
27#include <string.h>
28 
29/*
30 *  The original table from the application and our copy of it with
31 *  some changes.
32 */
33extern rtems_configuration_table Configuration;
34rtems_configuration_table  BSP_Configuration;
35char *rtems_progname;
36
37/*
38 * Location of 'VME' access
39 */
40#define VME_ONE_BASE    0x30000000
41#define VME_TWO_BASE    0x31000000
42
43/*
44 * Cacheable areas
45 */
46#define SDRAM_BASE      0
47#define SDRAM_SIZE      (16*1024*1024)
48#define FLASH_BASE      0xFF800000
49#define FLASH_SIZE      (8*1024*1024)
50
51/*
52 * CPU-space access
53 */
54#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
55#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
56#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
57
58/*
59 * Read/write copy of common cache
60 *   Split I/D cache
61 *   Allow CPUSHL to invalidate a cache line
62 *   Enable buffered writes
63 *   No burst transfers on non-cacheable accesses
64 *   Default cache mode is *disabled* (cache only ACRx areas)
65 */
66static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
67                              MCF5XXX_CACR_DBWE |
68                              MCF5XXX_CACR_DCM;
69/*
70 * Cannot be frozen
71 */
72void _CPU_cache_freeze_data(void) {}
73void _CPU_cache_unfreeze_data(void) {}
74void _CPU_cache_freeze_instruction(void) {}
75void _CPU_cache_unfreeze_instruction(void) {}
76
77/*
78 * Write-through data cache -- flushes are unnecessary
79 */
80void _CPU_cache_flush_1_data_line(const void *d_addr) {}
81void _CPU_cache_flush_entire_data(void) {}
82
83void _CPU_cache_enable_instruction(void)
84{
85    rtems_interrupt_level level;
86
87    rtems_interrupt_disable(level);
88    cacr_mode &= ~MCF5XXX_CACR_DIDI;
89    m68k_set_cacr(cacr_mode);
90    rtems_interrupt_enable(level);
91}
92
93void _CPU_cache_disable_instruction(void)
94{
95    rtems_interrupt_level level;
96
97    rtems_interrupt_disable(level);
98    cacr_mode |= MCF5XXX_CACR_DIDI;
99    m68k_set_cacr(cacr_mode);
100    rtems_interrupt_enable(level);
101}
102
103void _CPU_cache_invalidate_entire_instruction(void)
104{
105    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
106}
107
108void _CPU_cache_invalidate_1_instruction_line(const void *addr)
109{
110    /*
111     * Top half of cache is I-space
112     */
113    addr = (void *)((int)addr | 0x400);
114    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
115}
116
117void _CPU_cache_enable_data(void)
118{
119    rtems_interrupt_level level;
120
121    rtems_interrupt_disable(level);
122    cacr_mode &= ~MCF5XXX_CACR_DISD;
123    m68k_set_cacr(cacr_mode);
124    rtems_interrupt_enable(level);
125}
126
127void _CPU_cache_disable_data(void)
128{
129    rtems_interrupt_level level;
130
131    rtems_interrupt_disable(level);
132    rtems_interrupt_disable(level);
133    cacr_mode |= MCF5XXX_CACR_DISD;
134    m68k_set_cacr(cacr_mode);
135    rtems_interrupt_enable(level);
136}
137
138void _CPU_cache_invalidate_entire_data(void)
139{
140    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
141}
142
143void _CPU_cache_invalidate_1_data_line(const void *addr)
144{
145    /*
146     * Bottom half of cache is D-space
147     */
148    addr = (void *)((int)addr & ~0x400);
149    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
150}
151
152/*
153 *  Use the shared implementations of the following routines
154 */
155void bsp_postdriver_hook(void);
156void bsp_libc_init( void *, uint32_t, int );
157void bsp_pretasking_hook(void);      /* m68k version */
158
159/*
160 *  bsp_start
161 *
162 *  This routine does the bulk of the system initialisation.
163 */
164void bsp_start( void )
165{
166  extern char _WorkspaceBase[];
167  extern char _RamSize[];
168  extern unsigned long  _M68k_Ramsize;
169
170  _M68k_Ramsize = (unsigned long)_RamSize;    /* RAM size set in linker script */
171
172  /*
173   *  Allocate the memory for the RTEMS Work Space.  This can come from
174   *  a variety of places: hard coded address, malloc'ed from outside
175   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
176   *  typically done by stock BSPs) by subtracting the required amount
177   *  of work space from the last physical address on the CPU board.
178   */
179
180  /*
181   *  Need to "allocate" the memory for the RTEMS Workspace and
182   *  tell the RTEMS configuration where it is.  This memory is
183   *  not malloc'ed.  It is just "pulled from the air".
184   */
185
186  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
187
188  /*
189   * Invalidate the cache and disable it
190   */
191  m68k_set_acr0(0);
192  m68k_set_acr1(0);
193  m68k_set_cacr(MCF5XXX_CACR_CINV);
194
195  /*
196   * Cache SDRAM and FLASH
197   */
198  m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
199                MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
200                MCF5XXX_ACR_EN                |
201                MCF5XXX_ACR_BWE               |
202                MCF5XXX_ACR_SM_IGNORE);
203
204  /*
205   * Enable the cache
206   */
207  m68k_set_cacr(cacr_mode);
208}
209
210uint32_t get_CPU_clock_speed(void)
211{
212  extern char _CPUClockSpeed[];
213  return( (uint32_t)_CPUClockSpeed);
214}
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