1 | /* |
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2 | * BSP startup |
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3 | * |
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4 | * This routine starts the application. It includes application, |
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5 | * board, and monitor specific initialization and configuration. |
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6 | * The generic CPU dependent initialization has been performed |
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7 | * before this routine is invoked. |
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8 | * |
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9 | * Author: |
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10 | * David Fiddes, D.J@fiddes.surfaid.org |
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11 | * http://www.calm.hw.ac.uk/davidf/coldfire/ |
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12 | * |
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13 | * COPYRIGHT (c) 1989-1998. |
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14 | * On-Line Applications Research Corporation (OAR). |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #include <bsp.h> |
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22 | #include <string.h> |
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23 | |
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24 | /* |
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25 | * Cacheable areas |
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26 | */ |
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27 | #define SDRAM_BASE 0 |
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28 | #define SDRAM_SIZE (16*1024*1024) |
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29 | #define FLASH_BASE 0xFF800000 |
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30 | #define FLASH_SIZE (8*1024*1024) |
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31 | |
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32 | /* |
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33 | * CPU-space access |
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34 | */ |
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35 | #define m68k_set_acr0(_acr0) __asm__ volatile ("movec %0,%%acr0" : : "d" (_acr0)) |
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36 | #define m68k_set_acr1(_acr1) __asm__ volatile ("movec %0,%%acr1" : : "d" (_acr1)) |
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37 | |
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38 | /* |
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39 | * Read/write copy of common cache |
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40 | * Split I/D cache |
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41 | * Allow CPUSHL to invalidate a cache line |
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42 | * Enable buffered writes |
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43 | * No burst transfers on non-cacheable accesses |
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44 | * Default cache mode is *disabled* (cache only ACRx areas) |
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45 | */ |
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46 | static uint32_t cacr_mode = MCF5XXX_CACR_CENB | |
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47 | MCF5XXX_CACR_DBWE | |
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48 | MCF5XXX_CACR_DCM; |
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49 | /* |
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50 | * Cannot be frozen |
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51 | */ |
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52 | void _CPU_cache_freeze_data(void) {} |
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53 | void _CPU_cache_unfreeze_data(void) {} |
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54 | void _CPU_cache_freeze_instruction(void) {} |
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55 | void _CPU_cache_unfreeze_instruction(void) {} |
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56 | |
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57 | /* |
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58 | * Write-through data cache -- flushes are unnecessary |
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59 | */ |
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60 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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61 | void _CPU_cache_flush_entire_data(void) {} |
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62 | |
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63 | void _CPU_cache_enable_instruction(void) |
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64 | { |
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65 | rtems_interrupt_level level; |
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66 | |
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67 | rtems_interrupt_disable(level); |
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68 | cacr_mode &= ~MCF5XXX_CACR_DIDI; |
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69 | m68k_set_cacr(cacr_mode); |
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70 | rtems_interrupt_enable(level); |
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71 | } |
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72 | |
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73 | void _CPU_cache_disable_instruction(void) |
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74 | { |
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75 | rtems_interrupt_level level; |
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76 | |
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77 | rtems_interrupt_disable(level); |
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78 | cacr_mode |= MCF5XXX_CACR_DIDI; |
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79 | m68k_set_cacr(cacr_mode); |
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80 | rtems_interrupt_enable(level); |
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81 | } |
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82 | |
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83 | void _CPU_cache_invalidate_entire_instruction(void) |
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84 | { |
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85 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); |
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86 | } |
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87 | |
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88 | void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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89 | { |
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90 | /* |
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91 | * Top half of cache is I-space |
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92 | */ |
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93 | addr = (void *)((int)addr | 0x400); |
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94 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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95 | } |
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96 | |
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97 | void _CPU_cache_enable_data(void) |
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98 | { |
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99 | rtems_interrupt_level level; |
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100 | |
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101 | rtems_interrupt_disable(level); |
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102 | cacr_mode &= ~MCF5XXX_CACR_DISD; |
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103 | m68k_set_cacr(cacr_mode); |
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104 | rtems_interrupt_enable(level); |
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105 | } |
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106 | |
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107 | void _CPU_cache_disable_data(void) |
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108 | { |
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109 | rtems_interrupt_level level; |
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110 | |
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111 | rtems_interrupt_disable(level); |
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112 | rtems_interrupt_disable(level); |
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113 | cacr_mode |= MCF5XXX_CACR_DISD; |
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114 | m68k_set_cacr(cacr_mode); |
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115 | rtems_interrupt_enable(level); |
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116 | } |
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117 | |
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118 | void _CPU_cache_invalidate_entire_data(void) |
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119 | { |
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120 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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121 | } |
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122 | |
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123 | void _CPU_cache_invalidate_1_data_line(const void *addr) |
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124 | { |
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125 | /* |
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126 | * Bottom half of cache is D-space |
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127 | */ |
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128 | addr = (void *)((int)addr & ~0x400); |
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129 | __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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130 | } |
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131 | |
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132 | /* |
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133 | * bsp_start |
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134 | * |
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135 | * This routine does the bulk of the system initialisation. |
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136 | */ |
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137 | void bsp_start( void ) |
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138 | { |
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139 | /* |
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140 | * Invalidate the cache and disable it |
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141 | */ |
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142 | m68k_set_acr0(0); |
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143 | m68k_set_acr1(0); |
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144 | m68k_set_cacr(MCF5XXX_CACR_CINV); |
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145 | |
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146 | /* |
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147 | * Cache SDRAM and FLASH |
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148 | */ |
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149 | m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE) | |
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150 | MCF5XXX_ACR_AM(SDRAM_SIZE-1) | |
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151 | MCF5XXX_ACR_EN | |
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152 | MCF5XXX_ACR_BWE | |
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153 | MCF5XXX_ACR_SM_IGNORE); |
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154 | |
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155 | /* |
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156 | * Enable the cache |
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157 | */ |
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158 | m68k_set_cacr(cacr_mode); |
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159 | } |
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160 | |
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161 | extern char _CPUClockSpeed[]; |
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162 | |
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163 | uint32_t get_CPU_clock_speed(void) |
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164 | { |
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165 | return( (uint32_t)_CPUClockSpeed); |
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166 | } |
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