source: rtems/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c @ a474e3c

4.104.114.84.9
Last change on this file since a474e3c was a474e3c, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 12, 2007 at 11:18:19 AM

2007-03-12 Joel Sherrill <joel@…>

  • include/coverhd.h, start/start.S, startup/bspclean.c, startup/bspstart.c, startup/linkcmds, startup/linkcmdsflash, startup/linkcmdsram: Correct license URL and/or fix mistake in copyright notice. Both of these mistakes appear to be from code submitted after these changes were made previously.
  • Property mode set to 100644
File size: 5.7 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *
16 *  The license and distribution terms for this file may be
17 *  found in the file LICENSE in this distribution or at
18 *
19 *  http://www.rtems.com/license/LICENSE.
20 *
21 *  $Id$
22 */
23
24#include <bsp.h>
25#include <rtems/libio.h>
26#include <rtems/libcsupport.h>
27#include <string.h>
28 
29/*
30 *  The original table from the application and our copy of it with
31 *  some changes.
32 */
33extern rtems_configuration_table Configuration;
34rtems_configuration_table  BSP_Configuration;
35rtems_cpu_table Cpu_table;
36char *rtems_progname;
37
38/*
39 * Location of 'VME' access
40 */
41#define VME_ONE_BASE    0x30000000
42#define VME_TWO_BASE    0x31000000
43
44/*
45 * Cacheable areas
46 */
47#define SDRAM_BASE      0
48#define SDRAM_SIZE      (16*1024*1024)
49#define FLASH_BASE      0xFF800000
50#define FLASH_SIZE      (8*1024*1024)
51
52/*
53 * CPU-space access
54 */
55#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
56#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
57#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
58
59/*
60 * Read/write copy of common cache
61 *   Split I/D cache
62 *   Allow CPUSHL to invalidate a cache line
63 *   Enable buffered writes
64 *   No burst transfers on non-cacheable accesses
65 *   Default cache mode is *disabled* (cache only ACRx areas)
66 */
67static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
68                              MCF5XXX_CACR_DBWE |
69                              MCF5XXX_CACR_DCM;
70/*
71 * Cannot be frozen
72 */
73void _CPU_cache_freeze_data(void) {}
74void _CPU_cache_unfreeze_data(void) {}
75void _CPU_cache_freeze_instruction(void) {}
76void _CPU_cache_unfreeze_instruction(void) {}
77
78/*
79 * Write-through data cache -- flushes are unnecessary
80 */
81void _CPU_cache_flush_1_data_line(const void *d_addr) {}
82void _CPU_cache_flush_entire_data(void) {}
83
84void _CPU_cache_enable_instruction(void)
85{
86    rtems_interrupt_level level;
87
88    rtems_interrupt_disable(level);
89    cacr_mode &= ~MCF5XXX_CACR_DIDI;
90    m68k_set_cacr(cacr_mode);
91    rtems_interrupt_enable(level);
92}
93
94void _CPU_cache_disable_instruction(void)
95{
96    rtems_interrupt_level level;
97
98    rtems_interrupt_disable(level);
99    cacr_mode |= MCF5XXX_CACR_DIDI;
100    m68k_set_cacr(cacr_mode);
101    rtems_interrupt_enable(level);
102}
103
104void _CPU_cache_invalidate_entire_instruction(void)
105{
106    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
107}
108
109void _CPU_cache_invalidate_1_instruction_line(const void *addr)
110{
111    /*
112     * Top half of cache is I-space
113     */
114    addr = (void *)((int)addr | 0x400);
115    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
116}
117
118void _CPU_cache_enable_data(void)
119{
120    rtems_interrupt_level level;
121
122    rtems_interrupt_disable(level);
123    cacr_mode &= ~MCF5XXX_CACR_DISD;
124    m68k_set_cacr(cacr_mode);
125    rtems_interrupt_enable(level);
126}
127
128void _CPU_cache_disable_data(void)
129{
130    rtems_interrupt_level level;
131
132    rtems_interrupt_disable(level);
133    rtems_interrupt_disable(level);
134    cacr_mode |= MCF5XXX_CACR_DISD;
135    m68k_set_cacr(cacr_mode);
136    rtems_interrupt_enable(level);
137}
138
139void _CPU_cache_invalidate_entire_data(void)
140{
141    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
142}
143
144void _CPU_cache_invalidate_1_data_line(const void *addr)
145{
146    /*
147     * Bottom half of cache is D-space
148     */
149    addr = (void *)((int)addr & ~0x400);
150    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
151}
152
153/*
154 *  Use the shared implementations of the following routines
155 */
156void bsp_postdriver_hook(void);
157void bsp_libc_init( void *, uint32_t, int );
158void bsp_pretasking_hook(void);                 /* m68k version */
159
160/*
161 *  bsp_start
162 *
163 *  This routine does the bulk of the system initialisation.
164 */
165void bsp_start( void )
166{
167  extern char _WorkspaceBase[];
168  extern char _RamSize[];
169  extern unsigned long  _M68k_Ramsize;
170
171  _M68k_Ramsize = (unsigned long)_RamSize;              /* RAM size set in linker script */
172
173  /*
174   *  Allocate the memory for the RTEMS Work Space.  This can come from
175   *  a variety of places: hard coded address, malloc'ed from outside
176   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
177   *  typically done by stock BSPs) by subtracting the required amount
178   *  of work space from the last physical address on the CPU board.
179   */
180
181  /*
182   *  Need to "allocate" the memory for the RTEMS Workspace and
183   *  tell the RTEMS configuration where it is.  This memory is
184   *  not malloc'ed.  It is just "pulled from the air".
185   */
186
187  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
188
189  /*
190   *  initialize the CPU table for this BSP
191   */
192  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
193  Cpu_table.postdriver_hook = bsp_postdriver_hook;
194  Cpu_table.interrupt_stack_size = 4096;
195  Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
196
197    /*
198     * Invalidate the cache and disable it
199     */
200    m68k_set_acr0(0);
201    m68k_set_acr1(0);
202    m68k_set_cacr(MCF5XXX_CACR_CINV);
203
204    /*
205     * Cache SDRAM and FLASH
206     */
207    m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
208                  MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
209                  MCF5XXX_ACR_EN                |
210                  MCF5XXX_ACR_BWE               |
211                  MCF5XXX_ACR_SM_IGNORE);
212
213    /*
214     * Enable the cache
215     */
216    m68k_set_cacr(cacr_mode);
217
218}
219
220uint32_t get_CPU_clock_speed(void)
221{
222    extern char _CPUClockSpeed[];
223    return( (uint32_t)_CPUClockSpeed);
224}
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