source: rtems/c/src/lib/libbsp/m68k/av5282/startup/bspstart.c @ 6ea100c1

4.104.114.9
Last change on this file since 6ea100c1 was 6ea100c1, checked in by Joel Sherrill <joel.sherrill@…>, on May 12, 2008 at 6:43:55 PM

2008-05-12 Joel Sherrill <joel.sherrill@…>

  • startup/bspstart.c: Refactored and renamed initialization routines to rtems_initialize_data_structures, rtems_initialize_before_drivers, rtems_initialize_device_drivers, and rtems_initialize_start_multitasking. This opened the sequence up so that bootcard() could provide a more robust and flexible framework which is easier to explain and understand. This also lays the groundwork for sharing the division of available memory between the RTEMS workspace and heap and the C library initialization across all BSPs.
  • Property mode set to 100644
File size: 5.1 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *
16 *  The license and distribution terms for this file may be
17 *  found in the file LICENSE in this distribution or at
18 *
19 *  http://www.rtems.com/license/LICENSE.
20 *
21 *  $Id$
22 */
23
24#include <bsp.h>
25#include <rtems/libio.h>
26#include <rtems/libcsupport.h>
27#include <string.h>
28 
29/*
30 * Location of 'VME' access
31 */
32#define VME_ONE_BASE    0x30000000
33#define VME_TWO_BASE    0x31000000
34
35/*
36 * Cacheable areas
37 */
38#define SDRAM_BASE      0
39#define SDRAM_SIZE      (16*1024*1024)
40#define FLASH_BASE      0xFF800000
41#define FLASH_SIZE      (8*1024*1024)
42
43/*
44 * CPU-space access
45 */
46#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
47#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
48#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
49
50/*
51 * Read/write copy of common cache
52 *   Split I/D cache
53 *   Allow CPUSHL to invalidate a cache line
54 *   Enable buffered writes
55 *   No burst transfers on non-cacheable accesses
56 *   Default cache mode is *disabled* (cache only ACRx areas)
57 */
58static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
59                              MCF5XXX_CACR_DBWE |
60                              MCF5XXX_CACR_DCM;
61/*
62 * Cannot be frozen
63 */
64void _CPU_cache_freeze_data(void) {}
65void _CPU_cache_unfreeze_data(void) {}
66void _CPU_cache_freeze_instruction(void) {}
67void _CPU_cache_unfreeze_instruction(void) {}
68
69/*
70 * Write-through data cache -- flushes are unnecessary
71 */
72void _CPU_cache_flush_1_data_line(const void *d_addr) {}
73void _CPU_cache_flush_entire_data(void) {}
74
75void _CPU_cache_enable_instruction(void)
76{
77    rtems_interrupt_level level;
78
79    rtems_interrupt_disable(level);
80    cacr_mode &= ~MCF5XXX_CACR_DIDI;
81    m68k_set_cacr(cacr_mode);
82    rtems_interrupt_enable(level);
83}
84
85void _CPU_cache_disable_instruction(void)
86{
87    rtems_interrupt_level level;
88
89    rtems_interrupt_disable(level);
90    cacr_mode |= MCF5XXX_CACR_DIDI;
91    m68k_set_cacr(cacr_mode);
92    rtems_interrupt_enable(level);
93}
94
95void _CPU_cache_invalidate_entire_instruction(void)
96{
97    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
98}
99
100void _CPU_cache_invalidate_1_instruction_line(const void *addr)
101{
102    /*
103     * Top half of cache is I-space
104     */
105    addr = (void *)((int)addr | 0x400);
106    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
107}
108
109void _CPU_cache_enable_data(void)
110{
111    rtems_interrupt_level level;
112
113    rtems_interrupt_disable(level);
114    cacr_mode &= ~MCF5XXX_CACR_DISD;
115    m68k_set_cacr(cacr_mode);
116    rtems_interrupt_enable(level);
117}
118
119void _CPU_cache_disable_data(void)
120{
121    rtems_interrupt_level level;
122
123    rtems_interrupt_disable(level);
124    rtems_interrupt_disable(level);
125    cacr_mode |= MCF5XXX_CACR_DISD;
126    m68k_set_cacr(cacr_mode);
127    rtems_interrupt_enable(level);
128}
129
130void _CPU_cache_invalidate_entire_data(void)
131{
132    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
133}
134
135void _CPU_cache_invalidate_1_data_line(const void *addr)
136{
137    /*
138     * Bottom half of cache is D-space
139     */
140    addr = (void *)((int)addr & ~0x400);
141    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
142}
143
144/*
145 *  Use the shared implementations of the following routines
146 */
147void bsp_pretasking_hook(void);      /* m68k version */
148
149/*
150 *  bsp_start
151 *
152 *  This routine does the bulk of the system initialisation.
153 */
154void bsp_start( void )
155{
156  extern char _WorkspaceBase[];
157  extern char _RamSize[];
158  extern unsigned long  _M68k_Ramsize;
159
160  _M68k_Ramsize = (unsigned long)_RamSize;    /* RAM size set in linker script */
161
162  /*
163   *  Allocate the memory for the RTEMS Work Space.  This can come from
164   *  a variety of places: hard coded address, malloc'ed from outside
165   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
166   *  typically done by stock BSPs) by subtracting the required amount
167   *  of work space from the last physical address on the CPU board.
168   */
169
170  /*
171   *  Need to "allocate" the memory for the RTEMS Workspace and
172   *  tell the RTEMS configuration where it is.  This memory is
173   *  not malloc'ed.  It is just "pulled from the air".
174   */
175
176  Configuration.work_space_start = (void *)_WorkspaceBase;
177
178  /*
179   * Invalidate the cache and disable it
180   */
181  m68k_set_acr0(0);
182  m68k_set_acr1(0);
183  m68k_set_cacr(MCF5XXX_CACR_CINV);
184
185  /*
186   * Cache SDRAM and FLASH
187   */
188  m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
189                MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
190                MCF5XXX_ACR_EN                |
191                MCF5XXX_ACR_BWE               |
192                MCF5XXX_ACR_SM_IGNORE);
193
194  /*
195   * Enable the cache
196   */
197  m68k_set_cacr(cacr_mode);
198}
199
200uint32_t get_CPU_clock_speed(void)
201{
202  extern char _CPUClockSpeed[];
203  return( (uint32_t)_CPUClockSpeed);
204}
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