1 | /* |
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2 | * BSP startup |
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3 | * |
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4 | * This routine starts the application. It includes application, |
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5 | * board, and monitor specific initialization and configuration. |
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6 | * The generic CPU dependent initialization has been performed |
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7 | * before this routine is invoked. |
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8 | * |
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9 | * Author: |
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10 | * David Fiddes, D.J@fiddes.surfaid.org |
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11 | * http://www.calm.hw.ac.uk/davidf/coldfire/ |
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12 | * |
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13 | * COPYRIGHT (c) 1989-1998. |
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14 | * On-Line Applications Research Corporation (OAR). |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * |
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19 | * http://www.rtems.com/license/LICENSE. |
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20 | * |
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21 | * $Id$ |
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22 | */ |
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23 | |
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24 | #include <bsp.h> |
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25 | #include <rtems/libio.h> |
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26 | #include <rtems/libcsupport.h> |
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27 | #include <string.h> |
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28 | |
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29 | /* |
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30 | * Location of 'VME' access |
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31 | */ |
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32 | #define VME_ONE_BASE 0x30000000 |
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33 | #define VME_TWO_BASE 0x31000000 |
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34 | |
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35 | /* |
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36 | * Cacheable areas |
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37 | */ |
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38 | #define SDRAM_BASE 0 |
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39 | #define SDRAM_SIZE (16*1024*1024) |
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40 | #define FLASH_BASE 0xFF800000 |
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41 | #define FLASH_SIZE (8*1024*1024) |
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42 | |
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43 | /* |
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44 | * CPU-space access |
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45 | */ |
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46 | #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr)) |
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47 | #define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) |
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48 | #define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) |
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49 | |
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50 | /* |
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51 | * Read/write copy of common cache |
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52 | * Split I/D cache |
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53 | * Allow CPUSHL to invalidate a cache line |
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54 | * Enable buffered writes |
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55 | * No burst transfers on non-cacheable accesses |
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56 | * Default cache mode is *disabled* (cache only ACRx areas) |
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57 | */ |
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58 | static uint32_t cacr_mode = MCF5XXX_CACR_CENB | |
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59 | MCF5XXX_CACR_DBWE | |
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60 | MCF5XXX_CACR_DCM; |
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61 | /* |
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62 | * Cannot be frozen |
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63 | */ |
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64 | void _CPU_cache_freeze_data(void) {} |
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65 | void _CPU_cache_unfreeze_data(void) {} |
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66 | void _CPU_cache_freeze_instruction(void) {} |
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67 | void _CPU_cache_unfreeze_instruction(void) {} |
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68 | |
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69 | /* |
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70 | * Write-through data cache -- flushes are unnecessary |
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71 | */ |
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72 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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73 | void _CPU_cache_flush_entire_data(void) {} |
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74 | |
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75 | void _CPU_cache_enable_instruction(void) |
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76 | { |
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77 | rtems_interrupt_level level; |
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78 | |
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79 | rtems_interrupt_disable(level); |
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80 | cacr_mode &= ~MCF5XXX_CACR_DIDI; |
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81 | m68k_set_cacr(cacr_mode); |
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82 | rtems_interrupt_enable(level); |
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83 | } |
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84 | |
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85 | void _CPU_cache_disable_instruction(void) |
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86 | { |
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87 | rtems_interrupt_level level; |
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88 | |
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89 | rtems_interrupt_disable(level); |
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90 | cacr_mode |= MCF5XXX_CACR_DIDI; |
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91 | m68k_set_cacr(cacr_mode); |
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92 | rtems_interrupt_enable(level); |
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93 | } |
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94 | |
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95 | void _CPU_cache_invalidate_entire_instruction(void) |
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96 | { |
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97 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); |
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98 | } |
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99 | |
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100 | void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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101 | { |
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102 | /* |
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103 | * Top half of cache is I-space |
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104 | */ |
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105 | addr = (void *)((int)addr | 0x400); |
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106 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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107 | } |
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108 | |
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109 | void _CPU_cache_enable_data(void) |
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110 | { |
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111 | rtems_interrupt_level level; |
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112 | |
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113 | rtems_interrupt_disable(level); |
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114 | cacr_mode &= ~MCF5XXX_CACR_DISD; |
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115 | m68k_set_cacr(cacr_mode); |
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116 | rtems_interrupt_enable(level); |
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117 | } |
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118 | |
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119 | void _CPU_cache_disable_data(void) |
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120 | { |
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121 | rtems_interrupt_level level; |
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122 | |
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123 | rtems_interrupt_disable(level); |
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124 | rtems_interrupt_disable(level); |
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125 | cacr_mode |= MCF5XXX_CACR_DISD; |
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126 | m68k_set_cacr(cacr_mode); |
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127 | rtems_interrupt_enable(level); |
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128 | } |
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129 | |
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130 | void _CPU_cache_invalidate_entire_data(void) |
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131 | { |
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132 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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133 | } |
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134 | |
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135 | void _CPU_cache_invalidate_1_data_line(const void *addr) |
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136 | { |
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137 | /* |
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138 | * Bottom half of cache is D-space |
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139 | */ |
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140 | addr = (void *)((int)addr & ~0x400); |
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141 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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142 | } |
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143 | |
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144 | /* |
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145 | * These are used by bsp_start |
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146 | */ |
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147 | extern char _WorkspaceBase[]; |
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148 | extern char _RamSize[]; |
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149 | extern unsigned long _M68k_Ramsize; |
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150 | |
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151 | /* |
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152 | * bsp_start |
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153 | * |
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154 | * This routine does the bulk of the system initialisation. |
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155 | */ |
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156 | void bsp_start( void ) |
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157 | { |
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158 | _M68k_Ramsize = (unsigned long)_RamSize; /* RAM size set in linker script */ |
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159 | |
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160 | /* |
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161 | * Allocate the memory for the RTEMS Work Space. This can come from |
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162 | * a variety of places: hard coded address, malloc'ed from outside |
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163 | * RTEMS world (e.g. simulator or primitive memory manager), or (as |
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164 | * typically done by stock BSPs) by subtracting the required amount |
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165 | * of work space from the last physical address on the CPU board. |
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166 | */ |
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167 | |
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168 | /* |
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169 | * Need to "allocate" the memory for the RTEMS Workspace and |
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170 | * tell the RTEMS configuration where it is. This memory is |
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171 | * not malloc'ed. It is just "pulled from the air". |
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172 | */ |
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173 | |
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174 | Configuration.work_space_start = (void *)_WorkspaceBase; |
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175 | |
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176 | /* |
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177 | * Invalidate the cache and disable it |
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178 | */ |
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179 | m68k_set_acr0(0); |
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180 | m68k_set_acr1(0); |
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181 | m68k_set_cacr(MCF5XXX_CACR_CINV); |
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182 | |
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183 | /* |
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184 | * Cache SDRAM and FLASH |
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185 | */ |
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186 | m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE) | |
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187 | MCF5XXX_ACR_AM(SDRAM_SIZE-1) | |
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188 | MCF5XXX_ACR_EN | |
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189 | MCF5XXX_ACR_BWE | |
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190 | MCF5XXX_ACR_SM_IGNORE); |
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191 | |
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192 | /* |
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193 | * Enable the cache |
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194 | */ |
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195 | m68k_set_cacr(cacr_mode); |
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196 | } |
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197 | |
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198 | extern char _CPUClockSpeed[]; |
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199 | |
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200 | uint32_t get_CPU_clock_speed(void) |
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201 | { |
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202 | return( (uint32_t)_CPUClockSpeed); |
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203 | } |
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