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source: rtems/c/src/lib/libbsp/m68k/av5282/network/network.c @ 721fe34

4.115

Last change on this file since 721fe34 was 721fe34, checked in by Joel Sherrill <joel.sherrill@…>, on 05/31/12 at 20:34:36
Fix C files which had two semi-colons at EOL
Property mode set to `100644`
File size: 27.9 KB

Line
1	#include <bsp.h>
2	#include <stdio.h>
3	#include <errno.h>
4	#include <stdarg.h>
5	#include <string.h>
6	#include <rtems.h>
7	#include <rtems/error.h>
8	#include <rtems/rtems_bsdnet.h>
9
10	#include <sys/param.h>
11	#include <sys/mbuf.h>
12	#include <sys/socket.h>
13	#include <sys/sockio.h>
14
15	#include <net/ethernet.h>
16	#include <net/if.h>
17
18	#include <netinet/in.h>
19	#include <netinet/if_ether.h>
20
21
22	/*
23	* Number of interfaces supported by this driver
24	*/
25	#define NIFACES 1
26
27	#define FEC_INTC0_TX_VECTOR (64+23)
28	#define FEC_INTC0_RX_VECTOR (64+27)
29
30	#define FEC_INTC0_TX_VECTOR (64+23)
31	#define FEC_INTC0_RX_VECTOR (64+27)
32	#define MII_VECTOR (64+7) /* IRQ7* pin connected to external transceiver */
33	#define MII_EPPAR MCF5282_EPORT_EPPAR_EPPA7_LEVEL
34	#define MII_EPDDR MCF5282_EPORT_EPDDR_EPDD7
35	#define MII_EPIER MCF5282_EPORT_EPIER_EPIE7
36	#define MII_EPPDR MCF5282_EPORT_EPPDR_EPPD7
37	/*
38	* Default number of buffer descriptors set aside for this driver.
39	* The number of transmit buffer descriptors has to be quite large
40	* since a single frame often uses three or more buffer descriptors.
41	*/
42	#define RX_BUF_COUNT 32
43	#define TX_BUF_COUNT 20
44	#define TX_BD_PER_BUF 3
45
46	#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255")
47
48	/*
49	* RTEMS event used by interrupt handler to signal daemons.
50	* This must not be the same event used by the TCP/IP task synchronization.
51	*/
52	#define TX_INTERRUPT_EVENT RTEMS_EVENT_1
53	#define RX_INTERRUPT_EVENT RTEMS_EVENT_1
54
55	/*
56	* RTEMS event used to start transmit daemon.
57	* This must not be the same as INTERRUPT_EVENT.
58	*/
59	#define START_TRANSMIT_EVENT RTEMS_EVENT_2
60
61	/*
62	* Receive buffer size -- Allow for a full ethernet packet plus CRC (1518).
63	* Round off to nearest multiple of RBUF_ALIGN.
64	*/
65	#define MAX_MTU_SIZE 1518
66	#define RBUF_ALIGN 4
67	#define RBUF_SIZE ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN)
68
69	#if (MCLBYTES < RBUF_SIZE)
70	#error "Driver must have MCLBYTES > RBUF_SIZE"
71	#endif
72
73	typedef struct mcf5282BufferDescriptor_ {
74	volatile uint16_t status;
75	uint16_t length;
76	volatile void *buffer;
77	} mcf5282BufferDescriptor_t;
78
79	/*
80	* Per-device data
81	*/
82	struct mcf5282_enet_struct {
83	struct arpcom arpcom;
84	struct mbuf **rxMbuf;
85	struct mbuf **txMbuf;
86	int acceptBroadcast;
87	int rxBdCount;
88	int txBdCount;
89	int txBdHead;
90	int txBdTail;
91	int txBdActiveCount;
92	mcf5282BufferDescriptor_t *rxBdBase;
93	mcf5282BufferDescriptor_t *txBdBase;
94	rtems_id rxDaemonTid;
95	rtems_id txDaemonTid;
96
97	/*
98	* Statistics
99	*/
100	unsigned long rxInterrupts;
101	unsigned long txInterrupts;
102	unsigned long miiInterrupts;
103	unsigned long txRawWait;
104	unsigned long txRealign;
105	unsigned long txRealignDrop;
106	uint16_t mii_sr2;
107	};
108	static struct mcf5282_enet_struct enet_driver[NIFACES];
109
110	static int
111	getMII(int phyNumber, int regNumber);
112
113
114	static rtems_isr
115	mcf5282_fec_rx_interrupt_handler( rtems_vector_number v )
116	{
117	MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
118	MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
119	enet_driver[0].rxInterrupts++;
120	rtems_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
121	}
122
123	static rtems_isr
124	mcf5282_fec_tx_interrupt_handler( rtems_vector_number v )
125	{
126	MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
127	MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
128	enet_driver[0].txInterrupts++;
129	rtems_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
130	}
131
132	static rtems_isr
133	mcf5282_mii_interrupt_handler( rtems_vector_number v )
134	{
135	uint16_t sr2;
136
137	enet_driver[0].miiInterrupts++;
138	getMII(1, 19); /* Read and clear interrupt status bits */
139	enet_driver[0].mii_sr2 = sr2 = getMII(1, 17);
140	if (((sr2 & 0x200) != 0)
141	&& ((MCF5282_FEC_TCR & MCF5282_FEC_TCR_FDEN) == 0))
142	MCF5282_FEC_TCR \|= MCF5282_FEC_TCR_FDEN;
143	else if (((sr2 & 0x200) == 0)
144	&& ((MCF5282_FEC_TCR & MCF5282_FEC_TCR_FDEN) != 0))
145	MCF5282_FEC_TCR &= ~MCF5282_FEC_TCR_FDEN;
146	}
147
148	/*
149	* Allocate buffer descriptors from (non-cached) on-chip static RAM
150	* Ensure 128-bit (16-byte) alignment
151	*/
152	extern char __SRAMBASE[];
153
154	static mcf5282BufferDescriptor_t *
155	mcf5282_bd_allocate(unsigned int count)
156	{
157	static mcf5282BufferDescriptor_t bdp = (mcf5282BufferDescriptor_t )__SRAMBASE;
158	mcf5282BufferDescriptor_t *p = bdp;
159
160	bdp += count;
161	if ((int)bdp & 0xF)
162	bdp = (mcf5282BufferDescriptor_t )((char )bdp + (16 - ((int)bdp & 0xF)));
163	return p;
164	}
165
166
167	/*
168	* Read MII register
169	* Busy-waits, but transfer time should be short!
170	*/
171	static int
172	getMII(int phyNumber, int regNumber)
173	{
174	MCF5282_FEC_MMFR = (0x1 << 30) \|
175	(0x2 << 28) \|
176	(phyNumber << 23) \|
177	(regNumber << 18) \|
178	(0x2 << 16);
179	while ((MCF5282_FEC_EIR & MCF5282_FEC_EIR_MII) == 0);
180	MCF5282_FEC_EIR = MCF5282_FEC_EIR_MII;
181	return MCF5282_FEC_MMFR & 0xFFFF;
182	}
183
184
185	/*
186	* Write MII register
187	* Busy-waits, but transfer time should be short!
188	*/
189	static void
190	setMII(int phyNumber, int regNumber, int value)
191	{
192	MCF5282_FEC_MMFR = (0x1 << 30) \|
193	(0x1 << 28) \|
194	(phyNumber << 23) \|
195	(regNumber << 18) \|
196	(0x2 << 16) \|
197	(value & 0xFFFF);
198	while ((MCF5282_FEC_EIR & MCF5282_FEC_EIR_MII) == 0);
199	MCF5282_FEC_EIR = MCF5282_FEC_EIR_MII;
200	}
201
202	static void
203	mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
204	{
205	int i;
206	const unsigned char *hwaddr;
207	rtems_status_code status;
208	rtems_isr_entry old_handler;
209	uint32_t clock_speed = get_CPU_clock_speed();
210
211	/*
212	* Issue reset to FEC
213	*/
214	MCF5282_FEC_ECR = MCF5282_FEC_ECR_RESET;
215	rtems_task_wake_after(1);
216	MCF5282_FEC_ECR = 0;
217
218	/*
219	* Configuration of I/O ports is done outside of this function
220	*/
221	#if 0
222	imm->gpio.pbcnt \|= MCF5282_GPIO_PBCNT_SET_FEC; /* Set up port b FEC pins */
223	#endif
224
225	/*
226	* Set our physical address
227	*/
228	hwaddr = sc->arpcom.ac_enaddr;
229	MCF5282_FEC_PALR = (hwaddr[0] << 24) \| (hwaddr[1] << 16) \|
230	(hwaddr[2] << 8) \| (hwaddr[3] << 0);
231	MCF5282_FEC_PAUR = (hwaddr[4] << 24) \| (hwaddr[5] << 16);
232
233
234	/*
235	* Clear the hash table
236	*/
237	MCF5282_FEC_GAUR = 0;
238	MCF5282_FEC_GALR = 0;
239
240	/*
241	* Set up receive buffer size
242	*/
243	MCF5282_FEC_EMRBR = 1520; /* Standard Ethernet */
244
245	/*
246	* Allocate mbuf pointers
247	*/
248	sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
249	sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
250	if (!sc->rxMbuf \|\| !sc->txMbuf)
251	rtems_panic("No memory for mbuf pointers");
252
253	/*
254	* Set receiver and transmitter buffer descriptor bases
255	*/
256	sc->rxBdBase = mcf5282_bd_allocate(sc->rxBdCount);
257	sc->txBdBase = mcf5282_bd_allocate(sc->txBdCount);
258	MCF5282_FEC_ERDSR = (int)sc->rxBdBase;
259	MCF5282_FEC_ETDSR = (int)sc->txBdBase;
260
261	/*
262	* Set up Receive Control Register:
263	* Not promiscuous
264	* MII mode
265	* Full duplex
266	* No loopback
267	*/
268	MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) \|
269	MCF5282_FEC_RCR_MII_MODE;
270
271	/*
272	* Set up Transmit Control Register:
273	* Full duplex
274	* No heartbeat
275	*/
276	MCF5282_FEC_TCR = MCF5282_FEC_TCR_FDEN;
277
278	/*
279	* Initialize statistic counters
280	*/
281	MCF5282_FEC_MIBC = MCF5282_FEC_MIBC_MIB_DISABLE;
282	{
283	vuint32 *vuip = &MCF5282_FEC_RMON_T_DROP;
284	while (vuip <= &MCF5282_FEC_IEEE_R_OCTETS_OK)
285	*vuip++ = 0;
286	}
287	MCF5282_FEC_MIBC = 0;
288
289	/*
290	* Set MII speed to <= 2.5 MHz
291	*/
292	i = (clock_speed + 5000000 - 1) / 5000000;
293	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(i);
294
295	/*
296	* Set PHYS to 100 Mb/s, full duplex
297	*/
298	setMII(1, 0, 0x2100);
299	setMII(1, 4, 0x0181);
300	setMII(1, 0, 0x0000);
301	rtems_task_wake_after(2);
302	sc->mii_sr2 = getMII(1, 17);
303	setMII(1, 18, 0x0072);
304	setMII(1, 0, 0x1000);
305	/*
306	* Set up receive buffer descriptors
307	*/
308	for (i = 0 ; i < sc->rxBdCount ; i++)
309	(sc->rxBdBase + i)->status = 0;
310
311	/*
312	* Set up transmit buffer descriptors
313	*/
314	for (i = 0 ; i < sc->txBdCount ; i++) {
315	sc->txBdBase[i].status = 0;
316	sc->txMbuf[i] = NULL;
317	}
318	sc->txBdHead = sc->txBdTail = 0;
319	sc->txBdActiveCount = 0;
320
321	/*
322	* Set up interrupts
323	*/
324	status = rtems_interrupt_catch( mcf5282_fec_tx_interrupt_handler, FEC_INTC0_TX_VECTOR, &old_handler );
325	if (status != RTEMS_SUCCESSFUL)
326	rtems_panic ("Can't attach MCF5282 FEC TX interrupt handler: %s\n",
327	rtems_status_text(status));
328	status = rtems_interrupt_catch(mcf5282_fec_rx_interrupt_handler, FEC_INTC0_RX_VECTOR, &old_handler);
329	if (status != RTEMS_SUCCESSFUL)
330	rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n",
331	rtems_status_text(status));
332	MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) \|
333	MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY);
334	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 \| MCF5282_INTC_IMRL_MASKALL);
335	MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) \|
336	MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
337	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 \| MCF5282_INTC_IMRL_MASKALL);
338
339	status = rtems_interrupt_catch(mcf5282_mii_interrupt_handler, MII_VECTOR, &old_handler);
340	if (status != RTEMS_SUCCESSFUL)
341	rtems_panic ("Can't attach MCF5282 FEC MII interrupt handler: %s\n",
342	rtems_status_text(status));
343	MCF5282_EPORT_EPPAR &= ~MII_EPPAR;
344	MCF5282_EPORT_EPDDR &= ~MII_EPDDR;
345	MCF5282_EPORT_EPIER \|= MII_EPIER;
346	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT7 \| MCF5282_INTC_IMRL_MASKALL);
347	}
348
349	/*
350	* Soak up buffer descriptors that have been sent.
351	*/
352	void
353	fec_retire_tx_bd(volatile struct mcf5282_enet_struct *sc )
354	{
355	struct mbuf m, n;
356	uint16_t status;
357
358	while ((sc->txBdActiveCount != 0)
359	&& (((status = sc->txBdBase[sc->txBdTail].status) & MCF5282_FEC_TxBD_R) == 0)) {
360	if ((status & MCF5282_FEC_TxBD_TO1) == 0) {
361	m = sc->txMbuf[sc->txBdTail];
362	MFREE(m, n);
363	}
364	if (++sc->txBdTail == sc->txBdCount)
365	sc->txBdTail = 0;
366	sc->txBdActiveCount--;
367	}
368	}
369
370	static void
371	fec_rxDaemon (void *arg)
372	{
373	volatile struct mcf5282_enet_struct sc = (volatile struct mcf5282_enet_struct )arg;
374	struct ifnet ifp = (struct ifnet )&sc->arpcom.ac_if;
375	struct mbuf *m;
376	volatile uint16_t status;
377	volatile mcf5282BufferDescriptor_t *rxBd;
378	int rxBdIndex;
379
380	/*
381	* Allocate space for incoming packets and start reception
382	*/
383	for (rxBdIndex = 0 ; ;) {
384	rxBd = sc->rxBdBase + rxBdIndex;
385	MGETHDR(m, M_WAIT, MT_DATA);
386	MCLGET(m, M_WAIT);
387	m->m_pkthdr.rcvif = ifp;
388	sc->rxMbuf[rxBdIndex] = m;
389	rxBd->buffer = mtod(m, void *);
390	rxBd->status = MCF5282_FEC_RxBD_E;
391	if (++rxBdIndex == sc->rxBdCount) {
392	rxBd->status \|= MCF5282_FEC_RxBD_W;
393	break;
394	}
395	}
396
397	/*
398	* Input packet handling loop
399	*/
400	/* Indicate we have some ready buffers available */
401	MCF5282_FEC_RDAR = 0;
402
403	rxBdIndex = 0;
404	for (;;) {
405	rxBd = sc->rxBdBase + rxBdIndex;
406
407	/*
408	* Wait for packet if there's not one ready
409	*/
410	if ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
411	/*
412	* Clear old events.
413	*/
414	MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
415
416	/*
417	* Wait for packet to arrive.
418	* Check the buffer descriptor before waiting for the event.
419	* This catches the case when a packet arrives between the
420	* `if' above, and the clearing of the RXF bit in the EIR.
421	*/
422	while ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
423	rtems_event_set events;
424	int level;
425
426	rtems_interrupt_disable(level);
427	MCF5282_FEC_EIMR \|= MCF5282_FEC_EIMR_RXF;
428	rtems_interrupt_enable(level);
429	rtems_bsdnet_event_receive (RX_INTERRUPT_EVENT,
430	RTEMS_WAIT\|RTEMS_EVENT_ANY,
431	RTEMS_NO_TIMEOUT,
432	&events);
433	}
434	}
435
436	/*
437	* Check that packet is valid
438	*/
439	if (status & MCF5282_FEC_RxBD_L) {
440	/*
441	* Pass the packet up the chain.
442	* FIXME: Packet filtering hook could be done here.
443	*/
444	struct ether_header *eh;
445	int len = rxBd->length - sizeof(uint32_t);
446
447	/*
448	* Invalidate the cache and push the packet up.
449	* The cache is so small that it's more efficient to just
450	* invalidate the whole thing unless the packet is very small.
451	*/
452	m = sc->rxMbuf[rxBdIndex];
453	if (len < 128)
454	rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
455	else
456	rtems_cache_invalidate_entire_data();
457	m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
458	eh = mtod(m, struct ether_header *);
459	m->m_data += sizeof(struct ether_header);
460	ether_input(ifp, eh, m);
461
462	/*
463	* Allocate a new mbuf
464	*/
465	MGETHDR(m, M_WAIT, MT_DATA);
466	MCLGET(m, M_WAIT);
467	m->m_pkthdr.rcvif = ifp;
468	sc->rxMbuf[rxBdIndex] = m;
469	rxBd->buffer = mtod(m, void *);
470	}
471
472	/*
473	* Reenable the buffer descriptor
474	*/
475	rxBd->status = (status & MCF5282_FEC_RxBD_W) \| MCF5282_FEC_RxBD_E;
476	MCF5282_FEC_RDAR = 0;
477
478	/*
479	* Move to next buffer descriptor
480	*/
481	if (++rxBdIndex == sc->rxBdCount)
482	rxBdIndex = 0;
483	}
484	}
485
486	static void
487	fec_sendpacket(struct ifnet ifp, struct mbuf m)
488	{
489	struct mcf5282_enet_struct *sc = ifp->if_softc;
490	volatile mcf5282BufferDescriptor_t firstTxBd, txBd;
491	int nAdded;
492	uint16_t status;
493
494	/*
495	* Free up buffer descriptors
496	*/
497	fec_retire_tx_bd(sc);
498
499	/*
500	* Set up the transmit buffer descriptors.
501	* No need to pad out short packets since the
502	* hardware takes care of that automatically.
503	* No need to copy the packet to a contiguous buffer
504	* since the hardware is capable of scatter/gather DMA.
505	*/
506	nAdded = 0;
507	firstTxBd = sc->txBdBase + sc->txBdHead;
508
509	while(m != NULL) {
510	/*
511	* Wait for buffer descriptor to become available
512	*/
513	if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
514	/*
515	* Clear old events.
516	*/
517	MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
518
519	/*
520	* Wait for buffer descriptor to become available.
521	* Check for buffer descriptors before waiting for the event.
522	* This catches the case when a buffer became available between
523	* the `if' above, and the clearing of the TXF bit in the EIR.
524	*/
525	fec_retire_tx_bd(sc);
526	while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
527	rtems_event_set events;
528	int level;
529
530	rtems_interrupt_disable(level);
531	MCF5282_FEC_EIMR \|= MCF5282_FEC_EIMR_TXF;
532	rtems_interrupt_enable(level);
533	sc->txRawWait++;
534	rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT,
535	RTEMS_WAIT\|RTEMS_EVENT_ANY,
536	RTEMS_NO_TIMEOUT,
537	&events);
538	fec_retire_tx_bd(sc);
539	}
540	}
541
542	/*
543	* Don't set the READY flag on the first fragment
544	* until the whole packet has been readied.
545	*/
546	status = nAdded ? MCF5282_FEC_TxBD_R : 0;
547
548	/*
549	* The IP fragmentation routine in ip_output
550	* can produce fragments with zero length.
551	*/
552	if (m->m_len){
553	char p = mtod(m, char );
554	int offset = (int) p & 0x3;
555	txBd = sc->txBdBase + sc->txBdHead;
556	if (offset == 0) {
557	txBd->buffer = p;
558	txBd->length = m->m_len;
559	sc->txMbuf[sc->txBdHead] = m;
560	m = m->m_next;
561	}
562	else {
563	/*
564	* Stupid FEC can't handle misaligned data!
565	* Move offending bytes to a local buffer.
566	* Use buffer descriptor TO1 bit to indicate this.
567	*/
568	int nmove = 4 - offset;
569	char d = (char )&sc->txMbuf[sc->txBdHead];
570	status \|= MCF5282_FEC_TxBD_TO1;
571	sc->txRealign++;
572	if (nmove > m->m_len)
573	nmove = m->m_len;
574	m->m_data += nmove;
575	m->m_len -= nmove;
576	txBd->buffer = d;
577	txBd->length = nmove;
578	while (nmove--)
579	d++ = p++;
580	if (m->m_len == 0) {
581	struct mbuf *n;
582	sc->txRealignDrop++;
583	MFREE(m, n);
584	m = n;
585	}
586	}
587	nAdded++;
588	if (++sc->txBdHead == sc->txBdCount) {
589	status \|= MCF5282_FEC_TxBD_W;
590	sc->txBdHead = 0;
591	}
592	txBd->status = status;
593	}
594	else {
595	/*
596	* Just toss empty mbufs
597	*/
598	struct mbuf *n;
599	MFREE(m, n);
600	m = n;
601	}
602	}
603	if (nAdded) {
604	txBd->status = status \| MCF5282_FEC_TxBD_R
605	\| MCF5282_FEC_TxBD_L
606	\| MCF5282_FEC_TxBD_TC;
607	if (nAdded > 1)
608	firstTxBd->status \|= MCF5282_FEC_TxBD_R;
609	MCF5282_FEC_TDAR = 0;
610	sc->txBdActiveCount += nAdded;
611	}
612	}
613
614	void
615	fec_txDaemon(void *arg)
616	{
617	struct mcf5282_enet_struct sc = (struct mcf5282_enet_struct )arg;
618	struct ifnet *ifp = &sc->arpcom.ac_if;
619	struct mbuf *m;
620	rtems_event_set events;
621
622	for (;;) {
623	/*
624	* Wait for packet
625	*/
626	rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
627	RTEMS_EVENT_ANY \| RTEMS_WAIT,
628	RTEMS_NO_TIMEOUT,
629	&events);
630
631	/*
632	* Send packets till queue is empty
633	*/
634	for (;;) {
635	/*
636	* Get the next mbuf chain to transmit.
637	*/
638	IF_DEQUEUE(&ifp->if_snd, m);
639	if (!m)
640	break;
641	fec_sendpacket(ifp, m);
642	}
643	ifp->if_flags &= ~IFF_OACTIVE;
644	}
645	}
646
647
648	/*
649	* Send packet (caller provides header).
650	*/
651	static void
652	mcf5282_enet_start(struct ifnet *ifp)
653	{
654	struct mcf5282_enet_struct *sc = ifp->if_softc;
655
656	rtems_event_send(sc->txDaemonTid, START_TRANSMIT_EVENT);
657	ifp->if_flags \|= IFF_OACTIVE;
658	}
659
660	static void
661	fec_init(void *arg)
662	{
663	struct mcf5282_enet_struct *sc = arg;
664	struct ifnet *ifp = &sc->arpcom.ac_if;
665
666	if (sc->txDaemonTid == 0) {
667	/*
668	* Set up hardware
669	*/
670	mcf5282_fec_initialize_hardware(sc);
671
672	/*
673	* Start driver tasks
674	*/
675	sc->txDaemonTid = rtems_bsdnet_newproc("FECtx", 4096, fec_txDaemon, sc);
676	sc->rxDaemonTid = rtems_bsdnet_newproc("FECrx", 4096, fec_rxDaemon, sc);
677	}
678
679	/*
680	* Set flags appropriately
681	*/
682	if (ifp->if_flags & IFF_PROMISC)
683	MCF5282_FEC_RCR \|= MCF5282_FEC_RCR_PROM;
684	else
685	MCF5282_FEC_RCR &= ~MCF5282_FEC_RCR_PROM;
686
687	/*
688	* Tell the world that we're running.
689	*/
690	ifp->if_flags \|= IFF_RUNNING;
691
692	/*
693	* Enable receiver and transmitter
694	*/
695	MCF5282_FEC_ECR = MCF5282_FEC_ECR_ETHER_EN;
696	}
697
698
699	static void
700	fec_stop(struct mcf5282_enet_struct *sc)
701	{
702	struct ifnet *ifp = &sc->arpcom.ac_if;
703
704	ifp->if_flags &= ~IFF_RUNNING;
705
706	/*
707	* Shut down receiver and transmitter
708	*/
709	MCF5282_FEC_ECR = 0x0;
710	}
711
712	/*
713	* Show interface statistics
714	*/
715	static void
716	enet_stats(struct mcf5282_enet_struct *sc)
717	{
718	printf(" Rx Interrupts:%-10lu", sc->rxInterrupts);
719	printf("Rx Packet Count:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_PACKETS);
720	printf(" Rx Broadcast:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_BC_PKT);
721	printf(" Rx Multicast:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_MC_PKT);
722	printf("CRC/Align error:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_CRC_ALIGN);
723	printf(" Rx Undersize:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_UNDERSIZE);
724	printf(" Rx Oversize:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_OVERSIZE);
725	printf(" Rx Fragment:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_FRAG);
726	printf(" Rx Jabber:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_JAB);
727	printf(" Rx 64:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_P64);
728	printf(" Rx 65-127:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_P65T0127);
729	printf(" Rx 128-255:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_P128TO255);
730	printf(" Rx 256-511:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_P256TO511);
731	printf(" Rx 511-1023:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_P512TO1023);
732	printf(" Rx 1024-2047:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_R_P1024TO2047);
733	printf(" Rx >=2048:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_GTE2048);
734	printf(" Rx Octets:%-10lu", (uint32_t) MCF5282_FEC_RMON_R_OCTETS);
735	printf(" Rx Dropped:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_R_DROP);
736	printf(" Rx frame OK:%-10lu", (uint32_t) MCF5282_FEC_IEEE_R_FRAME_OK);
737	printf(" Rx CRC error:%-10lu", (uint32_t) MCF5282_FEC_IEEE_R_CRC);
738	printf(" Rx Align error:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_R_ALIGN);
739	printf(" FIFO Overflow:%-10lu", (uint32_t) MCF5282_FEC_IEEE_R_MACERR);
740	printf("Rx Pause Frames:%-10lu", (uint32_t) MCF5282_FEC_IEEE_R_FDXFC);
741	printf(" Rx Octets OK:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_R_OCTETS_OK);
742	printf(" Tx Interrupts:%-10lu", sc->txInterrupts);
743	printf("Tx Output Waits:%-10lu", sc->txRawWait);
744	printf("Tx mbuf realign:%-10lu\n", sc->txRealign);
745	printf("Tx realign drop:%-10lu", sc->txRealignDrop);
746	printf(" Tx Unaccounted:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_DROP);
747	printf("Tx Packet Count:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_PACKETS);
748	printf(" Tx Broadcast:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_BC_PKT);
749	printf(" Tx Multicast:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_MC_PKT);
750	printf("CRC/Align error:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_CRC_ALIGN);
751	printf(" Tx Undersize:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_UNDERSIZE);
752	printf(" Tx Oversize:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_OVERSIZE);
753	printf(" Tx Fragment:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_FRAG);
754	printf(" Tx Jabber:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_JAB);
755	printf(" Tx Collisions:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_COL);
756	printf(" Tx 64:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_P64);
757	printf(" Tx 65-127:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_P65TO127);
758	printf(" Tx 128-255:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_P128TO255);
759	printf(" Tx 256-511:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_P256TO511);
760	printf(" Tx 511-1023:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_P512TO1023);
761	printf(" Tx 1024-2047:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_P1024TO2047);
762	printf(" Tx >=2048:%-10lu\n", (uint32_t) MCF5282_FEC_RMON_T_P_GTE2048);
763	printf(" Tx Octets:%-10lu", (uint32_t) MCF5282_FEC_RMON_T_OCTETS);
764	printf(" Tx Dropped:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_DROP);
765	printf(" Tx Frame OK:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_T_FRAME_OK);
766	printf(" Tx 1 Collision:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_1COL);
767	printf("Tx >1 Collision:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_MCOL);
768	printf(" Tx Deferred:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_T_DEF);
769	printf(" Late Collision:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_LCOL);
770	printf(" Excessive Coll:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_EXCOL);
771	printf(" FIFO Underrun:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_T_MACERR);
772	printf(" Carrier Error:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_CSERR);
773	printf(" Tx SQE Error:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_SQE);
774	printf("Tx Pause Frames:%-10lu\n", (uint32_t) MCF5282_FEC_IEEE_T_FDXFC);
775	printf(" Tx Octets OK:%-10lu", (uint32_t) MCF5282_FEC_IEEE_T_OCTETS_OK);
776	printf(" MII interrupts:%-10lu\n", sc->miiInterrupts);
777
778	printf(" EIR:%8.8lx ", (uint32_t) MCF5282_FEC_EIR);
779	printf("EIMR:%8.8lx ", (uint32_t) MCF5282_FEC_EIMR);
780	printf("RDAR:%8.8lx ", (uint32_t) MCF5282_FEC_RDAR);
781	printf("TDAR:%8.8lx\n", (uint32_t) MCF5282_FEC_TDAR);
782	printf(" ECR:%8.8lx ", (uint32_t) MCF5282_FEC_ECR);
783	printf(" RCR:%8.8lx ", (uint32_t) MCF5282_FEC_RCR);
784	printf(" TCR:%8.8lx\n", (uint32_t) MCF5282_FEC_TCR);
785	printf("FRBR:%8.8lx ", (uint32_t) MCF5282_FEC_FRBR);
786	printf("FRSR:%8.8lx\n", (uint32_t) MCF5282_FEC_FRSR);
787	if (sc->txBdActiveCount != 0) {
788	int i, n;
789	/*
790	* Yes, there are races here with adding and retiring descriptors,
791	* but this diagnostic is more for when things have backed up.
792	*/
793	printf("Transmit Buffer Descriptors (Tail %d, Head %d, Unretired %d):\n",
794	sc->txBdTail,
795	sc->txBdHead,
796	sc->txBdActiveCount);
797	i = sc->txBdTail;
798	for (n = 0 ; n < sc->txBdCount ; n++) {
799	if ((sc->txBdBase[i].status & MCF5282_FEC_TxBD_R) != 0)
800	printf(" %3d: status:%4.4x length:%-4d buffer:%p\n",
801	i,
802	sc->txBdBase[i].status,
803	sc->txBdBase[i].length,
804	sc->txBdBase[i].buffer);
805	if (++i == sc->txBdCount)
806	i = 0;
807	}
808	}
809	}
810
811	static int
812	fec_ioctl(struct ifnet *ifp, ioctl_command_t command, caddr_t data)
813	{
814	struct mcf5282_enet_struct *sc = ifp->if_softc;
815	int error = 0;
816
817	switch (command) {
818	case SIOCGIFADDR:
819	case SIOCSIFADDR:
820	ether_ioctl(ifp, command, data);
821	break;
822
823	case SIOCSIFFLAGS:
824	switch (ifp->if_flags & (IFF_UP \| IFF_RUNNING)) {
825	case IFF_RUNNING:
826	fec_stop(sc);
827	break;
828
829	case IFF_UP:
830	fec_init(sc);
831	break;
832
833	case IFF_UP \| IFF_RUNNING:
834	fec_stop(sc);
835	fec_init(sc);
836	break;
837
838	default:
839	break;
840	}
841	break;
842
843	case SIO_RTEMS_SHOW_STATS:
844	enet_stats(sc);
845	break;
846
847	/*
848	* FIXME: All sorts of multicast commands need to be added here!
849	*/
850	default:
851	error = EINVAL;
852	break;
853	}
854	return error;
855	}
856
857	int
858	rtems_fec_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching )
859	{
860	struct mcf5282_enet_struct *sc;
861	struct ifnet *ifp;
862	int mtu;
863	int unitNumber;
864	char *unitName;
865	unsigned char *hwaddr;
866
867	/*
868	* Parse driver name
869	*/
870	if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
871	return 0;
872
873	/*
874	* Is driver free?
875	*/
876	if ((unitNumber <= 0) \|\| (unitNumber > NIFACES)) {
877	printf("Bad FEC unit number.\n");
878	return 0;
879	}
880	sc = &enet_driver[unitNumber - 1];
881	ifp = &sc->arpcom.ac_if;
882	if (ifp->if_softc != NULL) {
883	printf("Driver already in use.\n");
884	return 0;
885	}
886
887	/*
888	* Process options
889	*/
890	printf("%s%d: Ethernet address: ", unitName, unitNumber );
891	if (config->hardware_address) {
892	hwaddr = config->hardware_address;
893	printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
894	hwaddr[0], hwaddr[1], hwaddr[2],
895	hwaddr[3], hwaddr[4], hwaddr[5]);
896	memcpy(sc->arpcom.ac_enaddr, hwaddr, ETHER_ADDR_LEN);
897	} else {
898	printf("UNKNOWN\n");
899	}
900
901	if (config->mtu)
902	mtu = config->mtu;
903	else
904	mtu = ETHERMTU;
905	if (config->rbuf_count)
906	sc->rxBdCount = config->rbuf_count;
907	else
908	sc->rxBdCount = RX_BUF_COUNT;
909	if (config->xbuf_count)
910	sc->txBdCount = config->xbuf_count;
911	else
912	sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF;
913
914	sc->acceptBroadcast = !config->ignore_broadcast;
915
916	/*
917	* Set up network interface values
918	*/
919	ifp->if_softc = sc;
920	ifp->if_unit = unitNumber;
921	ifp->if_name = unitName;
922	ifp->if_mtu = mtu;
923	ifp->if_init = fec_init;
924	ifp->if_ioctl = fec_ioctl;
925	ifp->if_start = mcf5282_enet_start;
926	ifp->if_output = ether_output;
927	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX;
928	if (ifp->if_snd.ifq_maxlen == 0)
929	ifp->if_snd.ifq_maxlen = ifqmaxlen;
930
931	/*
932	* Attach the interface
933	*/
934	if_attach(ifp);
935	ether_ifattach(ifp);
936	return 1;
937	};
938

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