1 | /* |
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2 | * This file contains definitions for LatticeMico32 TSMAC (Tri-Speed MAC) |
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3 | * |
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4 | * COPYRIGHT (c) 1989-1999. |
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5 | * On-Line Applications Research Corporation (OAR). |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | * |
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11 | * $Id$ |
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12 | * |
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13 | * Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008, |
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14 | * Micro-Research Finland Oy |
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15 | */ |
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16 | |
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17 | #ifndef _BSPTSMAC_H |
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18 | #define _BSPTSMAC_H |
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19 | |
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20 | /* FIFO Registers */ |
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21 | |
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22 | #define LM32_TSMAC_RX_LEN_FIFO (0x000) |
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23 | #define LM32_TSMAC_RX_DATA_FIFO (0x004) |
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24 | #define LM32_TSMAC_TX_LEN_FIFO (0x008) |
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25 | #define LM32_TSMAC_TX_DATA_FIFO (0x00C) |
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26 | |
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27 | /* Control and Status Registers */ |
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28 | |
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29 | #define LM32_TSMAC_VERID (0x100) |
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30 | #define LM32_TSMAC_INTR_SRC (0x104) |
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31 | #define INTR_RX_SMRY (0x00020000) |
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32 | #define INTR_TX_SMRY (0x00010000) |
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33 | #define INTR_RX_FIFO_FULL (0x00001000) |
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34 | #define INTR_RX_ERROR (0x00000800) |
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35 | #define INTR_RX_FIFO_ERROR (0x00000400) |
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36 | #define INTR_RX_FIFO_ALMOST_FULL (0x00000200) |
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37 | #define INTR_RX_PKT_RDY (0x00000100) |
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38 | #define INTR_TX_FIFO_FULL (0x00000010) |
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39 | #define INTR_TX_DISCFRM (0x00000008) |
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40 | #define INTR_TX_FIFO_ALMOST_EMPTY (0x00000004) |
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41 | #define INTR_TX_FIFO_ALMOST_FULL (0x00000002) |
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42 | #define INTR_TX_PKT_SENT (0x00000001) |
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43 | #define LM32_TSMAC_INTR_ENB (0x108) |
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44 | #define INTR_ENB (0x00040000) |
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45 | #define LM32_TSMAC_RX_STATUS (0x10C) |
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46 | #define STAT_RX_FIFO_FULL (0x00000010) |
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47 | #define STAT_RX_ERROR (0x00000008) |
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48 | #define STAT_RX_FIFO_ERROR (0x00000004) |
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49 | #define STAT_RX_FIFO_ALMOST_FULL (0x00000002) |
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50 | #define STAT_RX_PKT_RDY (0x00000001) |
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51 | #define LM32_TSMAC_TX_STATUS (0x110) |
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52 | #define STAT_TX_FIFO_FULL (0x00000010) |
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53 | #define STAT_TX_DISCFRM (0x00000008) |
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54 | #define STAT_TX_FIFO_ALMOST_EMPTY (0x00000004) |
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55 | #define STAT_TX_FIFO_ALMOST_FULL (0x00000002) |
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56 | #define STAT_TX_PKT_SENT (0x00000001) |
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57 | #define LM32_TSMAC_RX_FRAMES_CNT (0x114) |
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58 | #define LM32_TSMAC_TX_FRAMES_CNT (0x118) |
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59 | #define LM32_TSMAC_RX_FIFO_TH (0x11C) |
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60 | #define LM32_TSMAC_TX_FIFO_TH (0x120) |
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61 | #define LM32_TSMAC_SYS_CTL (0x124) |
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62 | #define SYS_CTL_TX_FIFO_FLUSH (0x00000010) |
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63 | #define SYS_CTL_RX_FIFO_FLUSH (0x00000008) |
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64 | #define SYS_CTL_TX_SNDPAUSREQ (0x00000004) |
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65 | #define SYS_CTL_TX_FIFOCTRL (0x00000002) |
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66 | #define SYS_CTL_IGNORE_NEXT_PKT (0x00000001) |
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67 | #define LM32_TSMAC_PAUSE_TMR (0x128) |
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68 | |
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69 | /* Tri-Speed MAC Registers */ |
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70 | |
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71 | #define LM32_TSMAC_MAC_REGS_DATA (0x200) |
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72 | #define LM32_TSMAC_MAC_REGS_ADDR_RW (0x204) |
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73 | #define REGS_ADDR_WRITE (0x80000000) |
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74 | #define LM32_TSMAC_MODE_BYTE0 (0x000) |
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75 | #define MODE_TX_EN (1<<3) |
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76 | #define MODE_RX_EN (1<<2) |
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77 | #define MODE_FC_EN (1<<1) |
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78 | #define MODE_GBIT_EN (1<<0) |
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79 | #define LM32_TSMAC_TX_RX_CTL_BYTE0 (0x002) |
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80 | #define TX_RX_CTL_RECEIVE_SHORT (1<<8) |
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81 | #define TX_RX_CTL_RECEIVE_BRDCST (1<<7) |
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82 | #define TX_RX_CTL_DIS_RTRY (1<<6) |
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83 | #define TX_RX_CTL_HDEN (1<<5) |
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84 | #define TX_RX_CTL_RECEIVE_MLTCST (1<<4) |
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85 | #define TX_RX_CTL_RECEIVE_PAUSE (1<<3) |
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86 | #define TX_RX_CTL_TX_DIS_FCS (1<<2) |
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87 | #define TX_RX_CTL_DISCARD_FCS (1<<1) |
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88 | #define TX_RX_CTL_PRMS (1<<0) |
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89 | #define LM32_TSMAC_MAX_PKT_SIZE_BYTE0 (0x004) |
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90 | #define LM32_TSMAC_IPG_VAL_BYTE0 (0x008) |
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91 | #define LM32_TSMAC_MAC_ADDR_0_BYTE0 (0x00A) |
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92 | #define LM32_TSMAC_MAC_ADDR_1_BYTE0 (0x00C) |
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93 | #define LM32_TSMAC_MAC_ADDR_2_BYTE0 (0x00E) |
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94 | #define LM32_TSMAC_TX_RX_STS_BYTE0 (0x012) |
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95 | #define TX_RX_STS_RX_IDLE (1<<10) |
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96 | #define TX_RX_STS_TAGGED_FRAME (1<<9) |
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97 | #define TX_RX_STS_BRDCST_FRAME (1<<8) |
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98 | #define TX_RX_STS_MULTCST_FRAME (1<<7) |
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99 | #define TX_RX_STS_IPG_SHRINK (1<<6) |
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100 | #define TX_RX_STS_SHORT_FRAME (1<<5) |
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101 | #define TX_RX_STS_LONG_FRAME (1<<4) |
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102 | #define TX_RX_STS_ERROR_FRAME (1<<3) |
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103 | #define TX_RX_STS_CRC (1<<2) |
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104 | #define TX_RX_STS_PAUSE_FRAME (1<<1) |
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105 | #define TX_RX_STS_TX_IDLE (1<<0) |
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106 | #define LM32_TSMAC_GMII_MNG_CTL_BYTE0 (0x014) |
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107 | #define GMII_MNG_CTL_CMD_FIN (1<<14) |
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108 | #define GMII_MNG_CTL_READ_PHYREG (0) |
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109 | #define GMII_MNG_CTL_WRITE_PHYREG (1<<13) |
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110 | #define GMII_MNG_CTL_PHY_ADD_MASK (0x001f) |
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111 | #define GMII_MNG_CTL_PHY_ADD_SHIFT (8) |
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112 | #define GMII_MNG_CTL_REG_ADD_MASK (0x001f) |
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113 | #define GMII_MNG_CTL_REG_ADD_SHIFT (0) |
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114 | #define LM32_TSMAC_GMII_MNG_DAT_BYTE0 (0x016) |
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115 | #define LM32_TSMAC_MLT_TAB_0_BYTE0 (0x022) |
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116 | #define LM32_TSMAC_MLT_TAB_1_BYTE0 (0x024) |
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117 | #define LM32_TSMAC_MLT_TAB_2_BYTE0 (0x026) |
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118 | #define LM32_TSMAC_MLT_TAB_3_BYTE0 (0x028) |
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119 | #define LM32_TSMAC_MLT_TAB_4_BYTE0 (0x02A) |
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120 | #define LM32_TSMAC_MLT_TAB_5_BYTE0 (0x02C) |
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121 | #define LM32_TSMAC_MLT_TAB_6_BYTE0 (0x02E) |
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122 | #define LM32_TSMAC_MLT_TAB_7_BYTE0 (0x030) |
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123 | #define LM32_TSMAC_VLAN_TAG_BYTE0 (0x032) |
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124 | #define LM32_TSMAC_PAUS_OP_BYTE0 (0x034) |
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125 | |
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126 | /* Receive Statistics Counters */ |
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127 | |
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128 | #define LM32_TSMAC_RX_PKT_IGNR_CNT (0x300) |
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129 | #define LM32_TSMAC_RX_LEN_CHK_ERR_CNT (0x304) |
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130 | #define LM32_TSMAC_RX_LNG_FRM_CNT (0x308) |
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131 | #define LM32_TSMAC_RX_SHRT_FRM_CNT (0x30C) |
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132 | #define LM32_TSMAC_RX_IPG_VIOL_CNT (0x310) |
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133 | #define LM32_TSMAC_RX_CRC_ERR_CNT (0x314) |
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134 | #define LM32_TSMAC_RX_OK_PKT_CNT (0x318) |
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135 | #define LM32_TSMAC_RX_CTL_FRM_CNT (0x31C) |
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136 | #define LM32_TSMAC_RX_PAUSE_FRM_CNT (0x320) |
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137 | #define LM32_TSMAC_RX_MULTICAST_CNT (0x324) |
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138 | #define LM32_TSMAC_RX_BRDCAST_CNT (0x328) |
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139 | #define LM32_TSMAC_RX_VLAN_TAG_CNT (0x32C) |
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140 | #define LM32_TSMAC_RX_PRE_SHRINK_CNT (0x330) |
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141 | #define LM32_TSMAC_RX_DRIB_NIB_CNT (0x334) |
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142 | #define LM32_TSMAC_RX_UNSUP_OPCD_CNT (0x338) |
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143 | #define LM32_TSMAC_RX_BYTE_CNT (0x33C) |
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144 | |
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145 | /* Transmit Statistics Counters */ |
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146 | |
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147 | #define LM32_TSMAC_TX_UNICAST_CNT (0x400) |
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148 | #define LM32_TSMAC_TX_PAUSE_FRM_CNT (0x404) |
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149 | #define LM32_TSMAC_TX_MULTICAST_CNT (0x408) |
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150 | #define LM32_TSMAC_TX_BRDCAST_CNT (0x40C) |
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151 | #define LM32_TSMAC_TX_VLAN_TAG_CNT (0x410) |
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152 | #define LM32_TSMAC_TX_BAD_FCS_CNT (0x414) |
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153 | #define LM32_TSMAC_TX_JUMBO_CNT (0x418) |
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154 | #define LM32_TSMAC_TX_BYTE_CNT (0x41C) |
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155 | |
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156 | #ifdef CPU_U32_FIX |
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157 | void ipalign(struct mbuf *m); |
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158 | #endif |
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159 | |
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160 | #endif /* _BSPTSMAC_H */ |
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