1 | /* |
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2 | * This file contains definitions for LatticeMico32 TSMAC (Tri-Speed MAC) |
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3 | * |
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4 | * COPYRIGHT (c) 1989-1999. |
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5 | * On-Line Applications Research Corporation (OAR). |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | * |
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11 | * $Id$ |
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12 | * |
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13 | * Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008, |
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14 | * Micro-Research Finland Oy |
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15 | */ |
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16 | |
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17 | #define _KERNEL |
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18 | |
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19 | #include <rtems.h> |
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20 | #include <bsp.h> |
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21 | #include <stdio.h> |
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22 | #include <errno.h> |
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23 | #include <rtems/error.h> |
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24 | #include <rtems/rtems_bsdnet.h> |
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25 | |
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26 | #include <sys/param.h> |
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27 | #include <sys/mbuf.h> |
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28 | #include <sys/socket.h> |
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29 | #include <sys/sockio.h> |
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30 | |
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31 | #include <net/if.h> |
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32 | |
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33 | #include <netinet/in.h> |
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34 | #include <netinet/if_ether.h> |
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35 | |
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36 | #include "../include/system_conf.h" |
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37 | #include "tsmac.h" |
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38 | #include "dp83848phy.h" |
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39 | |
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40 | struct tsmac_softc { |
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41 | struct arpcom arpcom; |
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42 | void *ioaddr; |
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43 | rtems_id rxDaemonTid; |
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44 | rtems_id txDaemonTid; |
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45 | |
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46 | /* |
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47 | * Statistics |
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48 | */ |
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49 | int rxInterrupts; |
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50 | int rxPktIgnore; |
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51 | int rxLenCheckError; |
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52 | int rxLongFrame; |
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53 | int rxShortFrame; |
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54 | int rxIPGViolation; |
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55 | int rxCRCError; |
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56 | int rxOKPackets; |
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57 | int rxControlFrame; |
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58 | int rxPauseFrame; |
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59 | int rxMulticast; |
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60 | int rxBroadcast; |
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61 | int rxVLANTag; |
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62 | int rxPreShrink; |
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63 | int rxDribNib; |
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64 | int rxUnsupOPCD; |
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65 | int rxByteCnt; |
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66 | int rxFifoFull; |
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67 | |
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68 | int txInterrupts; |
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69 | int txUnicast; |
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70 | int txPauseFrame; |
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71 | int txMulticast; |
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72 | int txBroadcast; |
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73 | int txVLANTag; |
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74 | int txBadFCS; |
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75 | int txJumboCnt; |
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76 | int txByteCnt; |
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77 | int txLostCarrier; |
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78 | int txFifoFull; |
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79 | }; |
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80 | |
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81 | /* |
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82 | * Macros to access tsmac wrapper registers. |
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83 | */ |
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84 | |
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85 | static inline uint32_t tsmacread(unsigned int reg) |
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86 | { |
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87 | return *((uint32_t *)(TS_MAC_CORE_BASE_ADDRESS + reg)); |
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88 | } |
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89 | |
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90 | static inline void tsmacwrite(unsigned int reg, uint32_t value) |
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91 | { |
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92 | *((uint32_t *)(TS_MAC_CORE_BASE_ADDRESS + reg)) = value; |
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93 | } |
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94 | |
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95 | /* |
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96 | * tsmac is a wishbone to MAC wrapper. |
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97 | * The macros below access to MAC registers. |
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98 | */ |
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99 | |
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100 | static inline uint16_t tsmacregread(unsigned int reg) |
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101 | { |
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102 | tsmacwrite(LM32_TSMAC_MAC_REGS_ADDR_RW, reg); |
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103 | return *((uint16_t *)(TS_MAC_CORE_BASE_ADDRESS + LM32_TSMAC_MAC_REGS_DATA + 2)); |
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104 | } |
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105 | |
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106 | static inline void tsmacregwrite(unsigned int reg, uint16_t value) |
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107 | { |
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108 | *((uint16_t *)(TS_MAC_CORE_BASE_ADDRESS + LM32_TSMAC_MAC_REGS_DATA + 2)) = value; |
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109 | tsmacwrite(LM32_TSMAC_MAC_REGS_ADDR_RW, REGS_ADDR_WRITE | reg); |
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110 | } |
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111 | |
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112 | /* |
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113 | #define DEBUG 1 |
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114 | */ |
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115 | |
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116 | /* We support one interface */ |
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117 | |
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118 | #define TSMAC_NUM 1 |
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119 | #define TSMAC_NAME "TSMAC" |
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120 | #define TSMAC_MAC0 0x00 |
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121 | #define TSMAC_MAC1 0x0E |
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122 | #define TSMAC_MAC2 0xB2 |
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123 | #define TSMAC_MAC3 0x00 |
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124 | #define TSMAC_MAC4 0x00 |
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125 | #define TSMAC_MAC5 0x01 |
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126 | |
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127 | /* |
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128 | * The interrupt vector number associated with the tsmac device |
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129 | * driver. |
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130 | */ |
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131 | |
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132 | #define TSMAC_VECTOR ( TS_MAC_CORE_IRQ ) |
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133 | #define TSMAC_IRQMASK ( 1 << TSMAC_VECTOR ) |
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134 | |
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135 | rtems_isr tsmac_interrupt_handler(rtems_vector_number vector); |
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136 | |
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137 | extern lm32_isr_entry set_vector(rtems_isr_entry handler, |
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138 | rtems_vector_number vector, int type); |
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139 | |
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140 | /* |
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141 | * Macros to access PHY registers through the (G)MII |
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142 | */ |
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143 | |
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144 | uint16_t tsmacphyread(unsigned int reg) |
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145 | { |
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146 | tsmacregwrite(LM32_TSMAC_GMII_MNG_CTL_BYTE0, |
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147 | ((DEFAULT_PHY_ADDRESS & GMII_MNG_CTL_PHY_ADD_MASK) << |
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148 | GMII_MNG_CTL_PHY_ADD_SHIFT) | |
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149 | ((reg & GMII_MNG_CTL_REG_ADD_MASK) << |
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150 | GMII_MNG_CTL_REG_ADD_SHIFT) | |
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151 | GMII_MNG_CTL_READ_PHYREG); |
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152 | |
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153 | /* Wait for management interface to be ready */ |
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154 | while(!(tsmacregread(LM32_TSMAC_GMII_MNG_CTL_BYTE0) & GMII_MNG_CTL_CMD_FIN)); |
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155 | |
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156 | return tsmacregread(LM32_TSMAC_GMII_MNG_DAT_BYTE0); |
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157 | } |
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158 | |
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159 | void tsmacphywrite(unsigned int reg, uint16_t value) |
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160 | { |
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161 | tsmacregwrite(LM32_TSMAC_GMII_MNG_DAT_BYTE0, value); |
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162 | tsmacregwrite(LM32_TSMAC_GMII_MNG_CTL_BYTE0, |
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163 | ((DEFAULT_PHY_ADDRESS & GMII_MNG_CTL_PHY_ADD_MASK) << |
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164 | GMII_MNG_CTL_PHY_ADD_SHIFT) | |
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165 | ((reg & GMII_MNG_CTL_REG_ADD_MASK) << |
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166 | GMII_MNG_CTL_REG_ADD_SHIFT) | |
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167 | GMII_MNG_CTL_WRITE_PHYREG); |
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168 | |
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169 | /* Wait for management interface to be ready */ |
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170 | while(!(tsmacregread(LM32_TSMAC_GMII_MNG_CTL_BYTE0) & GMII_MNG_CTL_CMD_FIN)); |
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171 | } |
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172 | |
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173 | /* |
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174 | * Event definitions |
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175 | */ |
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176 | #define INTERRUPT_EVENT RTEMS_EVENT_1 |
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177 | #define START_TRANSMIT_EVENT RTEMS_EVENT_2 |
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178 | |
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179 | static struct tsmac_softc tsmac_softc[TSMAC_NUM]; |
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180 | |
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181 | #ifdef CPU_U32_FIX |
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182 | |
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183 | /* |
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184 | * Routine to align the received packet so that the ip header |
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185 | * is on a 32-bit boundary. Necessary for cpu's that do not |
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186 | * allow unaligned loads and stores and when the 32-bit DMA |
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187 | * mode is used. |
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188 | * |
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189 | * Transfers are done on word basis to avoid possibly slow byte |
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190 | * and half-word writes. |
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191 | * |
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192 | * Copied over from sonic.c driver |
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193 | */ |
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194 | |
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195 | void ipalign(struct mbuf *m) |
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196 | { |
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197 | unsigned int *first, *last, data; |
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198 | unsigned int tmp = 0; |
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199 | |
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200 | if ((((int) m->m_data) & 2) && (m->m_len)) { |
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201 | last = (unsigned int *) ((((int) m->m_data) + m->m_len + 8) & ~3); |
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202 | first = (unsigned int *) (((int) m->m_data) & ~3); |
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203 | tmp = *first << 16; |
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204 | first++; |
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205 | do { |
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206 | data = *first; |
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207 | *first = tmp | (data >> 16); |
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208 | tmp = data << 16; |
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209 | first++; |
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210 | } while (first <= last); |
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211 | |
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212 | m->m_data = (caddr_t)(((int) m->m_data) + 2); |
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213 | } |
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214 | } |
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215 | #endif |
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216 | |
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217 | /* |
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218 | * Receive task |
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219 | */ |
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220 | static void tsmac_rxDaemon(void *arg) |
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221 | { |
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222 | struct tsmac_softc *tsmac = (struct tsmac_softc *) arg; |
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223 | struct ifnet *ifp = &tsmac->arpcom.ac_if; |
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224 | rtems_event_set events; |
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225 | int rxq, count, len, data; |
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226 | |
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227 | #ifdef DEBUG |
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228 | printk(TSMAC_NAME ": tsmac_rxDaemon\n"); |
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229 | #endif |
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230 | |
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231 | for(;;) |
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232 | { |
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233 | rtems_bsdnet_event_receive( RTEMS_ALL_EVENTS, |
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234 | RTEMS_WAIT | RTEMS_EVENT_ANY, |
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235 | RTEMS_NO_TIMEOUT, |
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236 | &events); |
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237 | |
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238 | #ifdef DEBUG |
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239 | printk(TSMAC_NAME ": tsmac_rxDaemon wakeup\n"); |
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240 | #endif |
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241 | |
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242 | for (;;) |
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243 | { |
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244 | struct mbuf* m; |
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245 | struct ether_header* eh; |
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246 | uint32_t *buf; |
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247 | |
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248 | /* Get number of RX frames in RX FIFO */ |
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249 | rxq = tsmacread(LM32_TSMAC_RX_FRAMES_CNT); |
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250 | |
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251 | if (rxq == 0) |
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252 | break; |
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253 | |
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254 | /* Get lenght of frame */ |
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255 | len = tsmacread(LM32_TSMAC_RX_LEN_FIFO); |
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256 | #ifdef DEBUG |
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257 | printk(TSMAC_NAME ": Frames %d, len 0x%04x (%d)\n", |
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258 | rxq, len, len); |
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259 | #endif |
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260 | |
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261 | /* |
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262 | * Get memory for packet |
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263 | */ |
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264 | MGETHDR(m, M_WAIT, MT_DATA); |
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265 | MCLGET(m, M_WAIT); |
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266 | |
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267 | m->m_pkthdr.rcvif = ifp; |
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268 | |
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269 | buf = (uint32_t *) mtod(m, uint32_t*); |
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270 | for (count = 0; count < len; count += 4) |
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271 | { |
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272 | data = tsmacread(LM32_TSMAC_RX_DATA_FIFO); |
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273 | *buf++ = data; |
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274 | #ifdef DEBUG |
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275 | printk("%08x ", data); |
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276 | #endif |
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277 | } |
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278 | #ifdef DEBUG |
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279 | printk("\n"); |
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280 | #endif |
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281 | |
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282 | m->m_len = m->m_pkthdr.len = |
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283 | len - sizeof(uint32_t) - sizeof(struct ether_header); |
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284 | eh = mtod(m, struct ether_header*); |
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285 | m->m_data += sizeof(struct ether_header); |
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286 | |
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287 | #ifdef CPU_U32_FIX |
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288 | ipalign(m); /* Align packet on 32-bit boundary */ |
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289 | #endif |
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290 | |
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291 | /* Notify the ip stack that there is a new packet */ |
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292 | ether_input(ifp, eh, m); |
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293 | |
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294 | /* |
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295 | * Release RX frame |
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296 | */ |
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297 | } |
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298 | } |
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299 | } |
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300 | |
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301 | static unsigned char tsmac_txbuf[2048]; |
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302 | |
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303 | static void tsmac_sendpacket(struct ifnet *ifp, struct mbuf *m) |
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304 | { |
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305 | struct mbuf *nm = m; |
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306 | int len = 0, i; |
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307 | uint32_t *buf; |
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308 | |
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309 | #ifdef DEBUG |
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310 | printk(TSMAC_NAME ": tsmac_sendpacket\n"); |
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311 | #endif |
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312 | |
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313 | do |
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314 | { |
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315 | #ifdef DEBUG |
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316 | printk("mbuf: 0x%08x len %03x: ", nm->m_data, nm->m_len); |
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317 | for (i = 0; i < nm->m_len; i++) |
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318 | { |
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319 | printk("%02x", mtod(nm, unsigned char*)[i]); |
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320 | if (i & 1) |
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321 | printk(" "); |
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322 | } |
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323 | printk("\n"); |
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324 | #endif |
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325 | |
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326 | if (nm->m_len > 0) |
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327 | { |
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328 | memcpy(&tsmac_txbuf[len], (char *)nm->m_data, nm->m_len); |
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329 | len += nm->m_len; |
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330 | } |
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331 | } |
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332 | while ((nm = nm->m_next) != 0); |
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333 | |
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334 | buf = (uint32_t *) tsmac_txbuf; |
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335 | for (i = 0; i < len; i += 4) |
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336 | { |
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337 | #ifdef DEBUG |
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338 | printk("%08x", *buf); |
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339 | #endif |
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340 | tsmacwrite(LM32_TSMAC_TX_DATA_FIFO, *buf++); |
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341 | } |
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342 | #ifdef DEBUG |
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343 | printk("\n"); |
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344 | #endif |
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345 | |
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346 | /* |
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347 | * Enqueue TX frame |
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348 | */ |
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349 | tsmacwrite(LM32_TSMAC_TX_LEN_FIFO, len); |
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350 | } |
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351 | |
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352 | /* |
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353 | * Transmit task |
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354 | */ |
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355 | static void tsmac_txDaemon(void *arg) |
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356 | { |
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357 | struct tsmac_softc *tsmac = (struct tsmac_softc *) arg; |
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358 | struct ifnet *ifp = &tsmac->arpcom.ac_if; |
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359 | struct mbuf *m; |
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360 | rtems_event_set events; |
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361 | int txq; |
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362 | |
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363 | #ifdef DEBUG |
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364 | printk(TSMAC_NAME ": tsmac_txDaemon\n"); |
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365 | #endif |
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366 | |
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367 | for (;;) |
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368 | { |
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369 | /* |
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370 | * Wait for packet |
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371 | */ |
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372 | rtems_bsdnet_event_receive (START_TRANSMIT_EVENT | INTERRUPT_EVENT, |
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373 | RTEMS_EVENT_ANY | RTEMS_WAIT, |
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374 | RTEMS_NO_TIMEOUT, &events); |
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375 | #ifdef DEBUG |
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376 | printk(TSMAC_NAME ": tsmac_txDaemon event\n"); |
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377 | #endif |
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378 | for (;;) |
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379 | { |
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380 | /* |
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381 | * Here we should read amount of transmit memory available |
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382 | */ |
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383 | |
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384 | txq = 2048; |
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385 | |
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386 | if (txq < ifp->if_mtu) |
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387 | { |
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388 | /* |
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389 | * Here we need to enable transmit done IRQ |
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390 | */ |
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391 | #ifdef DEBUG |
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392 | printk(TSMAC_NAME ": TXMA %d < MTU + CW%d\n", txq, |
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393 | ifp->if_mtu); |
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394 | #endif |
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395 | break; |
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396 | } |
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397 | |
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398 | /* |
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399 | * Get the next mbuf chain to transmit. |
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400 | */ |
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401 | IF_DEQUEUE(&ifp->if_snd, m); |
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402 | #ifdef DEBUG |
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403 | printk(TSMAC_NAME ": mbuf %08x\n", (int) m); |
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404 | #endif |
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405 | if (!m) |
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406 | break; |
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407 | tsmac_sendpacket(ifp, m); |
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408 | |
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409 | m_freem(m); |
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410 | } |
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411 | ifp->if_flags &= ~IFF_OACTIVE; |
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412 | } |
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413 | } |
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414 | |
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415 | /* |
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416 | * Initialize TSMAC hardware |
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417 | */ |
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418 | void tsmac_init_hardware(struct tsmac_softc *tsmac) |
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419 | { |
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420 | unsigned char *mac_addr; |
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421 | int version_id, phyid, stat; |
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422 | |
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423 | #ifdef DEBUG |
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424 | printk(TSMAC_NAME ": tsmac_init_hardware\n"); |
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425 | #endif |
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426 | |
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427 | version_id = tsmacread(LM32_TSMAC_VERID); |
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428 | #ifdef DEBUG |
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429 | printk(TSMAC_NAME ": Version ID %08x\n", version_id); |
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430 | #endif |
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431 | |
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432 | #ifdef DEBUG |
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433 | printk(TSMAC_NAME ": MAC MODE %04x\n", tsmacregread(LM32_TSMAC_MODE_BYTE0)); |
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434 | printk(TSMAC_NAME ": MAC TX_RX_CTL %04x\n", tsmacregread(LM32_TSMAC_TX_RX_CTL_BYTE0)); |
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435 | printk(TSMAC_NAME ": MAC MAX_PKT_SIZE %04x\n", tsmacregread(LM32_TSMAC_MAX_PKT_SIZE_BYTE0)); |
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436 | printk(TSMAC_NAME ": MAC IPG_VAL %04x\n", tsmacregread(LM32_TSMAC_IPG_VAL_BYTE0)); |
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437 | printk(TSMAC_NAME ": MAC MAC_ADDR0 %04x\n", |
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438 | tsmacregread(LM32_TSMAC_MAC_ADDR_0_BYTE0)); |
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439 | printk(TSMAC_NAME ": MAC MAC_ADDR1 %04x\n", |
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440 | tsmacregread(LM32_TSMAC_MAC_ADDR_1_BYTE0)); |
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441 | printk(TSMAC_NAME ": MAC MAC_ADDR2 %04x\n", |
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442 | tsmacregread(LM32_TSMAC_MAC_ADDR_2_BYTE0)); |
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443 | printk(TSMAC_NAME ": MAC TX_RX_STS %04x\n", |
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444 | tsmacregread(LM32_TSMAC_TX_RX_STS_BYTE0)); |
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445 | #endif |
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446 | |
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447 | /* |
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448 | * Set our physical address |
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449 | */ |
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450 | mac_addr = tsmac->arpcom.ac_enaddr; |
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451 | tsmacregwrite(LM32_TSMAC_MAC_ADDR_0_BYTE0, (mac_addr[0] << 8) | mac_addr[1]); |
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452 | tsmacregwrite(LM32_TSMAC_MAC_ADDR_1_BYTE0, (mac_addr[2] << 8) | mac_addr[3]); |
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453 | tsmacregwrite(LM32_TSMAC_MAC_ADDR_2_BYTE0, (mac_addr[4] << 8) | mac_addr[5]); |
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454 | |
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455 | #ifdef DEBUG |
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456 | printk(TSMAC_NAME ": After setting MAC address.\n"); |
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457 | printk(TSMAC_NAME ": MAC MAC_ADDR0 %04x\n", |
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458 | tsmacregread(LM32_TSMAC_MAC_ADDR_0_BYTE0)); |
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459 | printk(TSMAC_NAME ": MAC MAC_ADDR1 %04x\n", |
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460 | tsmacregread(LM32_TSMAC_MAC_ADDR_1_BYTE0)); |
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461 | printk(TSMAC_NAME ": MAC MAC_ADDR2 %04x\n", |
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462 | tsmacregread(LM32_TSMAC_MAC_ADDR_2_BYTE0)); |
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463 | #endif |
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464 | |
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465 | /* |
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466 | * Configure PHY |
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467 | */ |
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468 | |
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469 | phyid = tsmacphyread(PHY_PHYIDR1); |
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470 | #ifdef DEBUG |
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471 | printk(TSMAC_NAME ": PHYIDR1 %08x\n", phyid); |
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472 | #endif |
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473 | phyid = tsmacphyread(PHY_PHYIDR2); |
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474 | #ifdef DEBUG |
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475 | printk(TSMAC_NAME ": PHYIDR2 %08x\n", phyid); |
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476 | #endif |
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477 | |
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478 | #ifdef TSMAC_FORCE_10BASET |
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479 | /* Force 10baseT mode, no AN, full duplex */ |
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480 | tsmacphywrite(PHY_BMCR, PHY_BMCR_DUPLEX_MODE); |
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481 | stat = tsmacphyread(PHY_BMCR); |
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482 | #ifdef DEBUG |
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483 | printk(TSMAC_NAME ": PHY BMCR %04x, wrote %04x\n", stat, |
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484 | PHY_BMCR_DUPLEX_MODE); |
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485 | #endif |
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486 | stat = tsmacphyread(PHY_BMSR); |
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487 | #ifdef DEBUG |
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488 | printk(TSMAC_NAME ": PHY BMSR %04x\n", stat); |
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489 | #endif |
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490 | /* Support for 10baseT modes only */ |
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491 | tsmacphywrite(PHY_ANAR, PHY_ANAR_10_FD | PHY_ANAR_10 | PHY_ANAR_SEL_DEF); |
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492 | stat = tsmacphyread(PHY_ANAR); |
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493 | #ifdef DEBUG |
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494 | printk(TSMAC_NAME ": PHY ANAR %04x, wrote %04x\n", stat, |
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495 | PHY_ANAR_10_FD | PHY_ANAR_10 | PHY_ANAR_SEL_DEF); |
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496 | #endif |
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497 | #endif /* TSMAC_FORCE_10BASET */ |
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498 | stat = tsmacphyread(PHY_PHYSTS); |
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499 | #ifdef DEBUG |
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500 | printk(TSMAC_NAME ": PHY PHYSTS %04x\n", stat); |
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501 | #endif |
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502 | |
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503 | /* Enable receive and transmit interrupts */ |
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504 | tsmacwrite(LM32_TSMAC_INTR_ENB, INTR_ENB | |
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505 | INTR_RX_SMRY | INTR_TX_SMRY | |
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506 | INTR_RX_PKT_RDY | INTR_TX_PKT_SENT); |
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507 | } |
---|
508 | |
---|
509 | /* |
---|
510 | * Initialize and start the device |
---|
511 | */ |
---|
512 | void tsmac_init(void *arg) |
---|
513 | { |
---|
514 | struct tsmac_softc *tsmac = &tsmac_softc[0]; |
---|
515 | struct ifnet *ifp = &tsmac->arpcom.ac_if; |
---|
516 | |
---|
517 | #ifdef DEBUG |
---|
518 | printk(TSMAC_NAME ": tsmac_init, tsmac->txDaemonTid = 0x%x\n", |
---|
519 | tsmac->txDaemonTid); |
---|
520 | #endif |
---|
521 | |
---|
522 | if (tsmac->txDaemonTid == 0) |
---|
523 | { |
---|
524 | /* |
---|
525 | * Initialize hardware |
---|
526 | */ |
---|
527 | tsmac_init_hardware(tsmac); |
---|
528 | |
---|
529 | /* |
---|
530 | * Start driver tasks |
---|
531 | */ |
---|
532 | tsmac->txDaemonTid = rtems_bsdnet_newproc ("TSMACtx", 4096, |
---|
533 | tsmac_txDaemon, tsmac); |
---|
534 | tsmac->rxDaemonTid = rtems_bsdnet_newproc ("TSMACrx", 4096, |
---|
535 | tsmac_rxDaemon, tsmac); |
---|
536 | /* |
---|
537 | * Setup interrupt handler |
---|
538 | */ |
---|
539 | set_vector( tsmac_interrupt_handler, TSMAC_VECTOR, 1 ); |
---|
540 | |
---|
541 | /* Interrupt line for TSMAC */ |
---|
542 | lm32_interrupt_unmask(TSMAC_IRQMASK); |
---|
543 | } |
---|
544 | |
---|
545 | ifp->if_flags |= IFF_RUNNING; |
---|
546 | |
---|
547 | /* |
---|
548 | * Receive broadcast |
---|
549 | */ |
---|
550 | |
---|
551 | tsmacregwrite(LM32_TSMAC_TX_RX_CTL_BYTE0, TX_RX_CTL_RECEIVE_BRDCST | |
---|
552 | TX_RX_CTL_RECEIVE_PAUSE); |
---|
553 | |
---|
554 | /* |
---|
555 | * Enable transmitter |
---|
556 | * Flow control enable |
---|
557 | * Enable receiver |
---|
558 | */ |
---|
559 | |
---|
560 | tsmacregwrite(LM32_TSMAC_MODE_BYTE0, MODE_TX_EN | MODE_RX_EN | MODE_FC_EN); |
---|
561 | |
---|
562 | /* |
---|
563 | * Wake up receive task to receive packets in queue |
---|
564 | */ |
---|
565 | rtems_event_send(tsmac->rxDaemonTid, INTERRUPT_EVENT); |
---|
566 | } |
---|
567 | |
---|
568 | void tsmac_stop(struct ifnet *ifp) |
---|
569 | { |
---|
570 | /* |
---|
571 | * Mask tsmac interrupts |
---|
572 | */ |
---|
573 | lm32_interrupt_mask(TSMAC_IRQMASK); |
---|
574 | |
---|
575 | ifp->if_flags &= ~IFF_RUNNING; |
---|
576 | |
---|
577 | /* |
---|
578 | * Disable transmitter and receiver |
---|
579 | */ |
---|
580 | tsmacregwrite(LM32_TSMAC_MODE_BYTE0, 0); |
---|
581 | } |
---|
582 | |
---|
583 | /* |
---|
584 | * Send packet |
---|
585 | */ |
---|
586 | void tsmac_start(struct ifnet *ifp) |
---|
587 | { |
---|
588 | struct tsmac_softc *tsmac = ifp->if_softc; |
---|
589 | |
---|
590 | rtems_event_send (tsmac->txDaemonTid, START_TRANSMIT_EVENT); |
---|
591 | ifp->if_flags |= IFF_OACTIVE; |
---|
592 | } |
---|
593 | |
---|
594 | void tsmac_stats(struct tsmac_softc *tsmac) |
---|
595 | { |
---|
596 | /* |
---|
597 | * Update counters from TSMAC MIB counters |
---|
598 | */ |
---|
599 | |
---|
600 | tsmac->rxPktIgnore = tsmacread(LM32_TSMAC_RX_PKT_IGNR_CNT); |
---|
601 | tsmac->rxLenCheckError = tsmacread(LM32_TSMAC_RX_LEN_CHK_ERR_CNT); |
---|
602 | tsmac->rxLongFrame = tsmacread(LM32_TSMAC_RX_LNG_FRM_CNT); |
---|
603 | tsmac->rxShortFrame = tsmacread(LM32_TSMAC_RX_SHRT_FRM_CNT); |
---|
604 | tsmac->rxIPGViolation = tsmacread(LM32_TSMAC_RX_IPG_VIOL_CNT); |
---|
605 | tsmac->rxCRCError = tsmacread(LM32_TSMAC_RX_CRC_ERR_CNT); |
---|
606 | tsmac->rxOKPackets = tsmacread(LM32_TSMAC_RX_OK_PKT_CNT); |
---|
607 | tsmac->rxControlFrame = tsmacread(LM32_TSMAC_RX_CTL_FRM_CNT); |
---|
608 | tsmac->rxPauseFrame = tsmacread(LM32_TSMAC_RX_PAUSE_FRM_CNT); |
---|
609 | tsmac->rxMulticast = tsmacread(LM32_TSMAC_RX_MULTICAST_CNT); |
---|
610 | tsmac->rxBroadcast = tsmacread(LM32_TSMAC_RX_BRDCAST_CNT); |
---|
611 | tsmac->rxVLANTag = tsmacread(LM32_TSMAC_RX_VLAN_TAG_CNT); |
---|
612 | tsmac->rxPreShrink = tsmacread(LM32_TSMAC_RX_PRE_SHRINK_CNT); |
---|
613 | tsmac->rxDribNib = tsmacread(LM32_TSMAC_RX_DRIB_NIB_CNT); |
---|
614 | tsmac->rxUnsupOPCD = tsmacread(LM32_TSMAC_RX_UNSUP_OPCD_CNT); |
---|
615 | tsmac->rxByteCnt = tsmacread(LM32_TSMAC_RX_BYTE_CNT); |
---|
616 | |
---|
617 | tsmac->txUnicast = tsmacread(LM32_TSMAC_TX_UNICAST_CNT); |
---|
618 | tsmac->txPauseFrame = tsmacread(LM32_TSMAC_TX_PAUSE_FRM_CNT); |
---|
619 | tsmac->txMulticast = tsmacread(LM32_TSMAC_TX_MULTICAST_CNT); |
---|
620 | tsmac->txBroadcast = tsmacread(LM32_TSMAC_TX_BRDCAST_CNT); |
---|
621 | tsmac->txVLANTag = tsmacread(LM32_TSMAC_TX_VLAN_TAG_CNT); |
---|
622 | tsmac->txBadFCS = tsmacread(LM32_TSMAC_TX_BAD_FCS_CNT); |
---|
623 | tsmac->txJumboCnt = tsmacread(LM32_TSMAC_TX_JUMBO_CNT); |
---|
624 | tsmac->txByteCnt = tsmacread(LM32_TSMAC_TX_BYTE_CNT); |
---|
625 | |
---|
626 | printk("RX Interrupts: %8d", tsmac->rxInterrupts); |
---|
627 | printk(" RX Len Chk Error: %8d", tsmac->rxLenCheckError); |
---|
628 | printk(" RX Long Frame: %8d\n", tsmac->rxLongFrame); |
---|
629 | printk("RX Short Frame: %8d", tsmac->rxShortFrame); |
---|
630 | printk(" RX IPG Violation: %8d", tsmac->rxIPGViolation); |
---|
631 | printk(" RX CRC Errors: %8d\n", tsmac->rxCRCError); |
---|
632 | printk("RX OK Packets: %8d", tsmac->rxOKPackets); |
---|
633 | printk(" RX Control Frame: %8d", tsmac->rxControlFrame); |
---|
634 | printk(" RX Pause Frame: %8d\n", tsmac->rxPauseFrame); |
---|
635 | printk("RX Multicast: %8d", tsmac->rxMulticast); |
---|
636 | printk(" RX Broadcast: %8d", tsmac->rxBroadcast); |
---|
637 | printk(" RX VLAN Tag: %8d\n", tsmac->rxVLANTag); |
---|
638 | printk("RX Pre Shrink: %8d", tsmac->rxPreShrink); |
---|
639 | printk(" RX Dribb. Nibble: %8d", tsmac->rxDribNib); |
---|
640 | printk(" RX Unsupp. OPCD: %8d\n", tsmac->rxUnsupOPCD); |
---|
641 | printk("RX Byte Count: %8d", tsmac->rxByteCnt); |
---|
642 | printk(" RX FIFO Full: %8d\n", tsmac->rxFifoFull); |
---|
643 | |
---|
644 | printk("TX Interrupts: %8d", tsmac->txInterrupts); |
---|
645 | printk(" TX Unicast: %8d", tsmac->txUnicast); |
---|
646 | printk(" TX Pause Frame: %8d\n", tsmac->txPauseFrame); |
---|
647 | printk("TX Multicast: %8d", tsmac->txMulticast); |
---|
648 | printk(" TX Broadcast: %8d", tsmac->txBroadcast); |
---|
649 | printk(" TX VLAN Tag: %8d\n", tsmac->txVLANTag); |
---|
650 | printk("TX Bad FSC: %8d", tsmac->txBadFCS); |
---|
651 | printk(" TX Jumbo Frame: %8d", tsmac->txJumboCnt); |
---|
652 | printk(" TX Byte Count: %8d\n", tsmac->txByteCnt); |
---|
653 | printk("TX FIFO Full: %8d\n", tsmac->txFifoFull); |
---|
654 | } |
---|
655 | |
---|
656 | /* |
---|
657 | * TSMAC ioctl handler |
---|
658 | */ |
---|
659 | |
---|
660 | int tsmac_ioctl(struct ifnet *ifp, ioctl_command_t command, caddr_t data) |
---|
661 | { |
---|
662 | struct tsmac_softc *tsmac = ifp->if_softc; |
---|
663 | int error = 0; |
---|
664 | |
---|
665 | switch (command) { |
---|
666 | case SIOCGIFADDR: |
---|
667 | case SIOCSIFADDR: |
---|
668 | ether_ioctl (ifp, command, data); |
---|
669 | break; |
---|
670 | |
---|
671 | case SIOCSIFFLAGS: |
---|
672 | switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { |
---|
673 | case IFF_RUNNING: |
---|
674 | tsmac_stop ((struct ifnet *) tsmac); |
---|
675 | break; |
---|
676 | |
---|
677 | case IFF_UP: |
---|
678 | tsmac_init ((struct ifnet *) tsmac); |
---|
679 | break; |
---|
680 | |
---|
681 | case IFF_UP | IFF_RUNNING: |
---|
682 | tsmac_stop ((struct ifnet *) tsmac); |
---|
683 | tsmac_init ((struct ifnet *) tsmac); |
---|
684 | break; |
---|
685 | |
---|
686 | default: |
---|
687 | break; |
---|
688 | } |
---|
689 | break; |
---|
690 | |
---|
691 | case SIO_RTEMS_SHOW_STATS: |
---|
692 | tsmac_stats (tsmac); |
---|
693 | break; |
---|
694 | |
---|
695 | default: |
---|
696 | error = EINVAL; |
---|
697 | break; |
---|
698 | } |
---|
699 | return error; |
---|
700 | } |
---|
701 | |
---|
702 | /* |
---|
703 | * Attach a TSMAC driver |
---|
704 | */ |
---|
705 | int rtems_tsmac_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching) |
---|
706 | { |
---|
707 | struct tsmac_softc *tsmac; |
---|
708 | struct ifnet *ifp; |
---|
709 | int mtu, i; |
---|
710 | int unit; |
---|
711 | char *unitName; |
---|
712 | |
---|
713 | if ((unit = rtems_bsdnet_parse_driver_name(config, &unitName)) < 0) |
---|
714 | { |
---|
715 | printk(TSMAC_NAME ": Driver name parsing failed.\n"); |
---|
716 | return 0; |
---|
717 | } |
---|
718 | |
---|
719 | if ((unit < 0) || (unit >= TSMAC_NUM)) |
---|
720 | { |
---|
721 | printk(TSMAC_NAME ": Bad unit number %d.\n", unit); |
---|
722 | return 0; |
---|
723 | } |
---|
724 | |
---|
725 | tsmac = &tsmac_softc[unit]; |
---|
726 | |
---|
727 | ifp = &tsmac->arpcom.ac_if; |
---|
728 | if (ifp->if_softc != NULL) |
---|
729 | { |
---|
730 | printk(TSMAC_NAME ": Driver already in use.\n"); |
---|
731 | return 0; |
---|
732 | } |
---|
733 | |
---|
734 | /* Base address for TSMAC */ |
---|
735 | if (config->bpar == 0) |
---|
736 | { |
---|
737 | printk(TSMAC_NAME ": Using default base address 0x%08x.\n", TS_MAC_CORE_BASE_ADDRESS); |
---|
738 | config->bpar = TS_MAC_CORE_BASE_ADDRESS; |
---|
739 | } |
---|
740 | tsmac->ioaddr = config->bpar; |
---|
741 | |
---|
742 | /* Hardware address for TSMAC */ |
---|
743 | if (config->hardware_address == 0) |
---|
744 | { |
---|
745 | printk(TSMAC_NAME ": Using default hardware address.\n"); |
---|
746 | tsmac->arpcom.ac_enaddr[0] = TSMAC_MAC0; |
---|
747 | tsmac->arpcom.ac_enaddr[1] = TSMAC_MAC1; |
---|
748 | tsmac->arpcom.ac_enaddr[2] = TSMAC_MAC2; |
---|
749 | tsmac->arpcom.ac_enaddr[3] = TSMAC_MAC3; |
---|
750 | tsmac->arpcom.ac_enaddr[4] = TSMAC_MAC4; |
---|
751 | tsmac->arpcom.ac_enaddr[5] = TSMAC_MAC5; |
---|
752 | } |
---|
753 | else |
---|
754 | memcpy(tsmac->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN); |
---|
755 | |
---|
756 | printk(TSMAC_NAME ": MAC address "); |
---|
757 | for (i = 0; i < ETHER_ADDR_LEN; i++) |
---|
758 | { |
---|
759 | printk("%02x", tsmac->arpcom.ac_enaddr[i]); |
---|
760 | if (i != ETHER_ADDR_LEN-1) |
---|
761 | printk(":"); |
---|
762 | else |
---|
763 | printk("\n"); |
---|
764 | } |
---|
765 | |
---|
766 | if (config->mtu) |
---|
767 | mtu = config->mtu; |
---|
768 | else |
---|
769 | mtu = ETHERMTU; |
---|
770 | |
---|
771 | /* |
---|
772 | * Set up network interface values |
---|
773 | */ |
---|
774 | ifp->if_softc = tsmac; |
---|
775 | ifp->if_unit = unit; |
---|
776 | ifp->if_name = unitName; |
---|
777 | ifp->if_mtu = mtu; |
---|
778 | ifp->if_init = tsmac_init; |
---|
779 | ifp->if_ioctl = tsmac_ioctl; |
---|
780 | ifp->if_start = tsmac_start; |
---|
781 | ifp->if_output = ether_output; |
---|
782 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; |
---|
783 | |
---|
784 | if (ifp->if_snd.ifq_maxlen == 0) |
---|
785 | ifp->if_snd.ifq_maxlen = ifqmaxlen; |
---|
786 | |
---|
787 | if_attach(ifp); |
---|
788 | ether_ifattach(ifp); |
---|
789 | |
---|
790 | return 1; |
---|
791 | } |
---|
792 | |
---|
793 | rtems_isr tsmac_interrupt_handler(rtems_vector_number vector) |
---|
794 | { |
---|
795 | struct tsmac_softc *tsmac = &tsmac_softc[0]; |
---|
796 | uint32_t irq_stat, rx_stat, tx_stat; |
---|
797 | |
---|
798 | irq_stat = tsmacread(LM32_TSMAC_INTR_SRC); |
---|
799 | if (irq_stat & INTR_RX_PKT_RDY) |
---|
800 | { |
---|
801 | tsmac->rxInterrupts++; |
---|
802 | rtems_event_send(tsmac->rxDaemonTid, INTERRUPT_EVENT); |
---|
803 | } |
---|
804 | |
---|
805 | if (irq_stat & INTR_TX_PKT_SENT) |
---|
806 | { |
---|
807 | tsmac->txInterrupts++; |
---|
808 | rtems_event_send(tsmac->txDaemonTid, INTERRUPT_EVENT); |
---|
809 | } |
---|
810 | |
---|
811 | rx_stat = tsmacread(LM32_TSMAC_RX_STATUS); |
---|
812 | if (rx_stat & STAT_RX_FIFO_FULL) |
---|
813 | tsmac->rxFifoFull++; |
---|
814 | |
---|
815 | tx_stat = tsmacread(LM32_TSMAC_TX_STATUS); |
---|
816 | if (tx_stat & STAT_TX_FIFO_FULL) |
---|
817 | tsmac->txFifoFull++; |
---|
818 | |
---|
819 | lm32_interrupt_ack(TSMAC_IRQMASK); |
---|
820 | } |
---|
821 | |
---|