1 | /** |
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2 | * @file |
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3 | * @ingroup lm32_tsmac |
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4 | * @brief LatticeMico32 TSMAC (Tri-Speed MAC) definitions |
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5 | */ |
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6 | |
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7 | /* |
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8 | * This file contains definitions for LatticeMico32 TSMAC (Tri-Speed MAC) |
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9 | * |
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10 | * COPYRIGHT (c) 1989-1999. |
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11 | * On-Line Applications Research Corporation (OAR). |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.com/license/LICENSE. |
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16 | * |
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17 | * Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008, |
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18 | * Micro-Research Finland Oy |
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19 | */ |
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20 | |
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21 | #ifndef _DP83848PHY_H |
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22 | #define _DP83848PHY_H |
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23 | |
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24 | #define DEFAULT_PHY_ADDRESS (0x01) |
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25 | |
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26 | #define PHY_BMCR (0x00) |
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27 | #define PHY_BMCR_RESET (1<<15) |
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28 | #define PHY_BMCR_LOOPBACK (1<<14) |
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29 | #define PHY_BMCR_SPEEDSEL (1<<13) |
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30 | #define PHY_BMCR_AN_ENA (1<<12) |
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31 | #define PHY_BMCR_PWRDWN (1<<11) |
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32 | #define PHY_BMCR_ISOLATE (1<<10) |
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33 | #define PHY_BMCR_RESTART_AN (1<<9) |
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34 | #define PHY_BMCR_DUPLEX_MODE (1<<8) |
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35 | #define PHY_BMCR_COLL_TEST (1<<7) |
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36 | #define PHY_BMSR (0x01) |
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37 | #define PHY_BMSR_100_T4 (1<<15) |
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38 | #define PHY_BMSR_100_TX_FD (1<<14) |
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39 | #define PHY_BMSR_100_TX_HD (1<<13) |
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40 | #define PHY_BMSR_10_T_FD (1<<12) |
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41 | #define PHY_BMSR_10_T_HD (1<<11) |
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42 | #define PHY_BMSR_PRESUP (1<<6) |
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43 | #define PHY_BMSR_AN_CMPL (1<<5) |
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44 | #define PHY_BMSR_REM_FLT (1<<4) |
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45 | #define PHY_BMSR_AN_AB (1<<3) |
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46 | #define PHY_BMSR_LINK_STAT (1<<2) |
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47 | #define PHY_BMSR_JABBDET (1<<1) |
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48 | #define PHY_BMSR_EXT_CAP (1<<0) |
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49 | #define PHY_PHYIDR1 (0x02) |
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50 | #define DEFAULT_PHYIDR1 (0x2000) |
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51 | #define PHY_PHYIDR2 (0x03) |
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52 | #define DEFAULT_PHYIDR2 (0x5C90) |
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53 | #define PHY_ANAR (0x04) |
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54 | #define PHY_ANAR_NP (1<<15) |
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55 | #define PHY_ANAR_RF (1<<13) |
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56 | #define PHY_ANAR_ASM_DIR (1<<11) |
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57 | #define PHY_ANAR_PAUSE (1<<10) |
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58 | #define PHY_ANAR_T4 (1<<9) |
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59 | #define PHY_ANAR_TX_FD (1<<8) |
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60 | #define PHY_ANAR_TX (1<<7) |
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61 | #define PHY_ANAR_10_FD (1<<6) |
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62 | #define PHY_ANAR_10 (1<<5) |
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63 | #define PHY_ANAR_SEL_MASK (0x0f) |
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64 | #define PHY_ANAR_SEL_SHIFT (0) |
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65 | #define PHY_ANAR_SEL_DEF (1) |
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66 | #define PHY_ANLPAR (0x05) |
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67 | #define PHY_ANLPAR_NP (1<<15) |
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68 | #define PHY_ANLPAR_ACK (1<<14) |
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69 | #define PHY_ANLPAR_RF (1<<13) |
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70 | #define PHY_ANLPAR_ASM_DIR (1<<11) |
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71 | #define PHY_ANLPAR_PAUSE (1<<10) |
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72 | #define PHY_ANLPAR_T4 (1<<9) |
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73 | #define PHY_ANLPAR_TX_FD (1<<8) |
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74 | #define PHY_ANLPAR_TX (1<<7) |
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75 | #define PHY_ANLPAR_10_FD (1<<6) |
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76 | #define PHY_ANLPAR_10 (1<<5) |
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77 | #define PHY_ANLPAR_SEL_MASK (0x0f) |
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78 | #define PHY_ANLPAR_SEL_SHIFT (0) |
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79 | #define PHY_ANLPARNP (0x05) |
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80 | #define PHY_ANLPARNP_NP (1<<15) |
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81 | #define PHY_ANLPARNP_ACK (1<<14) |
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82 | #define PHY_ANLPARNP_MP (1<<13) |
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83 | #define PHY_ANLPARNP_ACK2 (1<<12) |
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84 | #define PHY_ANLPARNP_TOGGLE (1<<11) |
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85 | #define PHY_ANLPARNP_CDE_MASK (0x03ff) |
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86 | #define PHY_ANER (0x06) |
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87 | #define PHY_ANER_PDF (1<<4) |
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88 | #define PHY_ANER_LP_NP_ABLE (1<<3) |
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89 | #define PHY_ANER_NP_ABLE (1<<2) |
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90 | #define PHY_ANER_PAGE_RX (1<<1) |
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91 | #define PHY_ANER_LP_AN_ABLE (1<<0) |
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92 | #define PHY_ANNPTR (0x07) |
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93 | #define PHY_ANNPTR_NP (1<<15) |
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94 | #define PHY_ANNPTR_MP (1<<13) |
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95 | #define PHY_ANNPTR_ACK2 (1<<12) |
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96 | #define PHY_ANNPTR_TOG_TX (1<<11) |
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97 | #define PHY_ANNPTR_CDE_MASK (0x03ff) |
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98 | #define PHY_PHYSTS (0x10) |
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99 | #define PHY_PHYSTS_MDIX_MDE (1<<14) |
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100 | #define PHY_PHYSTS_RCV_ERRL (1<<13) |
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101 | #define PHY_PHYSTS_POLSTAT (1<<12) |
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102 | #define PHY_PHYSTS_FCSL (1<<11) |
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103 | #define PHY_PHYSTS_SD (1<<10) |
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104 | #define PHY_PHYSTS_DESCL (1<<9) |
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105 | #define PHY_PHYSTS_PGREC (1<<8) |
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106 | #define PHY_PHYSTS_MIIIRQ (1<<7) |
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107 | #define PHY_PHYSTS_REM_FLT (1<<6) |
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108 | #define PHY_PHYSTS_JABBDET (1<<5) |
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109 | #define PHY_PHYSTS_AN_CMP (1<<4) |
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110 | #define PHY_PHYSTS_LOOPBACK (1<<3) |
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111 | #define PHY_PHYSTS_DUPLEX (1<<2) |
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112 | #define PHY_PHYSTS_SPEED (1<<1) |
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113 | #define PHY_PHYSTS_LINK (1<<0) |
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114 | #define PHY_MICR (0x11) |
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115 | #define PHY_MICR_TINT (1<<2) |
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116 | #define PHY_MICR_INTEN (1<<1) |
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117 | #define PHY_MICR_INT_OE (1<<0) |
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118 | #define PHY_MISR (0x12) |
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119 | #define PHY_MISR_ED_INT (1<<14) |
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120 | #define PHY_MISR_LINK_INT (1<<13) |
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121 | #define PHY_MISR_SPD_INT (1<<12) |
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122 | #define PHY_MISR_DUP_INT (1<<11) |
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123 | #define PHY_MISR_ANC_INT (1<<10) |
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124 | #define PHY_MISR_FHF_INT (1<<9) |
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125 | #define PHY_MISR_RHF_INT (1<<8) |
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126 | #define PHY_MISR_ED_INT_EN (1<<6) |
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127 | #define PHY_MISR_LINK_INT_EN (1<<5) |
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128 | #define PHY_MISR_SPD_INT_EN (1<<4) |
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129 | #define PHY_MISR_DUP_INT_EN (1<<3) |
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130 | #define PHY_MISR_ANC_INT_EN (1<<2) |
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131 | #define PHY_MISR_FHF_INT_EN (1<<1) |
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132 | #define PHY_MISR_RHF_INT_EN (1<<0) |
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133 | #define PHY_FCSCR (0x14) |
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134 | #define PHY_RECR (0x15) |
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135 | #define PHY_PCSR (0x16) |
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136 | #define PHY_PCSR_TQ_EN (1<<10) |
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137 | #define PHY_PCSR_SDFPMA (1<<9) |
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138 | #define PHY_PCSR_SD_OPT (1<<8) |
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139 | #define PHY_PCSR_DESC_TIME (1<<7) |
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140 | #define PHY_PCSR_F_100_OK (1<<5) |
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141 | #define PHY_PCSR_NRZI_BYPASS (1<<2) |
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142 | #define PHY_RBR (0x17) |
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143 | #define PHY_RBR_RMII_MODE (1<<5) |
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144 | #define PHY_RBR_RMII_REV1_0 (1<<4) |
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145 | #define PHY_RBR_RX_OVF_STS (1<<3) |
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146 | #define PHY_RBR_RX_UNF_STS (1<<2) |
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147 | #define PHY_RBR_ELAST_BUF1 (1<<1) |
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148 | #define PHY_RBR_ELAST_BUF0 (1<<0) |
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149 | #define PHY_LEDCR (0x18) |
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150 | #define PHY_LEDCR_DRV_SPDLED (1<<5) |
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151 | #define PHY_LEDCR_DRV_LNKLED (1<<4) |
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152 | #define PHY_LEDCR_DRV_ACTLED (1<<3) |
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153 | #define PHY_LEDCR_SPDLED (1<<2) |
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154 | #define PHY_LEDCR_LNKLED (1<<1) |
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155 | #define PHY_LEDCR_ACTLED (1<<0) |
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156 | #define PHY_PHYCR (0x19) |
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157 | #define PHY_PHYCR_MDIX_EN (1<<15) |
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158 | #define PHY_PHYCR_FORCE_MDIX (1<<14) |
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159 | #define PHY_PHYCR_PAUSE_RX (1<<13) |
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160 | #define PHY_PHYCR_PAUSE_TX (1<<12) |
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161 | #define PHY_PHYCR_BIST_FE (1<<11) |
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162 | #define PHY_PHYCR_PSR_15 (1<<10) |
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163 | #define PHY_PHYCR_BIST_STATUS (1<<9) |
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164 | #define PHY_PHYCR_BIST_START (1<<8) |
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165 | #define PHY_PHYCR_BP_STRETCH (1<<7) |
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166 | #define PHY_PHYCR_LED_CNFG1 (1<<6) |
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167 | #define PHY_PHYCR_LED_CNFG0 (1<<5) |
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168 | #define PHY_PHYCR_ADDR4 (1<<4) |
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169 | #define PHY_PHYCR_ADDR3 (1<<3) |
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170 | #define PHY_PHYCR_ADDR2 (1<<2) |
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171 | #define PHY_PHYCR_ADDR1 (1<<1) |
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172 | #define PHY_PHYCR_ADDR0 (1<<0) |
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173 | #define PHY_10BTSCR (0x1A) |
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174 | #define PHY_10BTSCR_SERIAL (1<<15) |
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175 | #define PHY_10BTSCR_SQ_MASK (0x07) |
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176 | #define PHY_10BTSCR_SQ_SHIFT (9) |
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177 | #define PHY_10BTSCR_LP_10_DIS (1<<8) |
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178 | #define PHY_10BTSCR_LP_DIS (1<<7) |
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179 | #define PHY_10BTSCR_FLINK_10 (1<<1) |
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180 | #define PHY_10BTSCR_POL (1<<4) |
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181 | #define PHY_10BTSCR_HB_DIS (1<<1) |
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182 | #define PHY_10BTSCR_JAB_DIS (1<<0) |
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183 | #define PHY_CDCTRL1 (0x1B) |
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184 | #define PHY_EDCR (0x1D) |
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185 | |
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186 | #endif /* _DP83848PHY_H */ |
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