source: rtems/c/src/lib/libbsp/lm32/milkymist/include/system_conf.h @ 03d184d0

4.11
Last change on this file since 03d184d0 was 03d184d0, checked in by Toma <radustoma@…>, on Dec 24, 2013 at 9:58:18 PM

lm32_milkymist: improve doxygen

Add doxygen to the header files in the /lm32/milymist/include directory.

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File size: 9.6 KB
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1/**
2 * @file
3 *
4 * @ingroup lm32_milkymist
5 *
6 * @brief System configuration.
7 */
8
9/*  system_conf.h
10 *  Global System conf
11 *
12 *  Milkymist port of RTEMS
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 *
18 *  COPYRIGHT (c) 2010, 2011 Sebastien Bourdeauducq
19 */
20
21#ifndef __SYSTEM_CONFIG_H_
22#define __SYSTEM_CONFIG_H_
23
24#define UART_BAUD_RATE          (115200)
25
26/* Clock frequency */
27#define MM_FREQUENCY            (0xe0001074)
28
29/* FML bridge */
30#define FMLBRG_FLUSH_BASE       (0xc8000000)
31#define FMLBRG_LINE_LENGTH      (32)
32#define FMLBRG_LINE_COUNT       (512)
33
34/* UART */
35#define MM_UART_RXTX            (0xe0000000)
36#define MM_UART_DIV             (0xe0000004)
37#define MM_UART_STAT            (0xe0000008)
38#define MM_UART_CTRL            (0xe000000c)
39
40#define UART_STAT_THRE          (0x1)
41#define UART_STAT_RX_EVT        (0x2)
42#define UART_STAT_TX_EVT        (0x4)
43
44#define UART_CTRL_RX_INT        (0x1)
45#define UART_CTRL_TX_INT        (0x2)
46#define UART_CTRL_THRU          (0x4)
47
48/* Timers */
49#define MM_TIMER1_COMPARE       (0xe0001024)
50#define MM_TIMER1_COUNTER       (0xe0001028)
51#define MM_TIMER1_CONTROL       (0xe0001020)
52
53#define MM_TIMER0_COMPARE       (0xe0001014)
54#define MM_TIMER0_COUNTER       (0xe0001018)
55#define MM_TIMER0_CONTROL       (0xe0001010)
56
57#define TIMER_ENABLE            (0x01)
58#define TIMER_AUTORESTART       (0x02)
59
60/* GPIO */
61#define MM_GPIO_IN              (0xe0001000)
62#define MM_GPIO_OUT             (0xe0001004)
63#define MM_GPIO_INTEN           (0xe0001008)
64
65#define GPIO_BTN1               (0x00000001)
66#define GPIO_BTN2               (0x00000002)
67#define GPIO_BTN3               (0x00000004)
68#define GPIO_PCBREV0            (0x00000008)
69#define GPIO_PCBREV1            (0x00000010)
70#define GPIO_PCBREV2            (0x00000020)
71#define GPIO_PCBREV3            (0x00000040)
72#define GPIO_LED1               (0x00000001)
73#define GPIO_LED2               (0x00000002)
74
75/* System ID and reset */
76#define MM_SYSTEM_ID            (0xe000107c)
77
78/* ICAP */
79#define MM_ICAP                 (0xe0001040)
80
81#define ICAP_READY              (0x01)
82#define ICAP_CE                 (0x10000)
83#define ICAP_WRITE              (0x20000)
84
85/* VGA */
86#define MM_VGA_RESET            (0xe0003000)
87
88#define MM_VGA_HRES             (0xe0003004)
89#define MM_VGA_HSYNC_START      (0xe0003008)
90#define MM_VGA_HSYNC_END        (0xe000300C)
91#define MM_VGA_HSCAN            (0xe0003010)
92
93#define MM_VGA_VRES             (0xe0003014)
94#define MM_VGA_VSYNC_START      (0xe0003018)
95#define MM_VGA_VSYNC_END        (0xe000301C)
96#define MM_VGA_VSCAN            (0xe0003020)
97
98#define MM_VGA_BASEADDRESS      (0xe0003024)
99#define MM_VGA_BASEADDRESS_ACT  (0xe0003028)
100
101#define MM_VGA_BURST_COUNT      (0xe000302C)
102
103#define MM_VGA_DDC              (0xe0003030)
104
105#define MM_VGA_CLKSEL           (0xe0003034)
106
107#define VGA_RESET               (0x01)
108#define VGA_DDC_SDAIN           (0x1)
109#define VGA_DDC_SDAOUT          (0x2)
110#define VGA_DDC_SDAOE           (0x4)
111#define VGA_DDC_SDC             (0x8)
112
113/* Ethernet */
114#define MM_MINIMAC_SETUP        (0xe0008000)
115#define MM_MINIMAC_MDIO         (0xe0008004)
116
117#define MM_MINIMAC_STATE0       (0xe0008008)
118#define MM_MINIMAC_COUNT0       (0xe000800C)
119#define MM_MINIMAC_STATE1       (0xe0008010)
120#define MM_MINIMAC_COUNT1       (0xe0008014)
121
122#define MM_MINIMAC_TXCOUNT      (0xe0008018)
123
124#define MINIMAC_RX0_BASE        (0xb0000000)
125#define MINIMAC_RX1_BASE        (0xb0000800)
126#define MINIMAC_TX_BASE         (0xb0001000)
127
128#define MINIMAC_SETUP_PHYRST    (0x1)
129
130#define MINIMAC_STATE_EMPTY     (0x0)
131#define MINIMAC_STATE_LOADED    (0x1)
132#define MINIMAC_STATE_PENDING   (0x2)
133
134/* AC97 */
135#define MM_AC97_CRCTL           (0xe0005000)
136
137#define AC97_CRCTL_RQEN         (0x01)
138#define AC97_CRCTL_WRITE        (0x02)
139
140#define MM_AC97_CRADDR          (0xe0005004)
141#define MM_AC97_CRDATAOUT       (0xe0005008)
142#define MM_AC97_CRDATAIN        (0xe000500C)
143
144#define MM_AC97_DCTL            (0xe0005010)
145#define MM_AC97_DADDRESS        (0xe0005014)
146#define MM_AC97_DREMAINING      (0xe0005018)
147
148#define MM_AC97_UCTL            (0xe0005020)
149#define MM_AC97_UADDRESS        (0xe0005024)
150#define MM_AC97_UREMAINING      (0xe0005028)
151
152#define AC97_SCTL_EN            (0x01)
153
154#define AC97_MAX_DMASIZE        (0x3fffc)
155
156/* SoftUSB */
157#define MM_SOFTUSB_CONTROL      (0xe000f000)
158
159#define SOFTUSB_CONTROL_RESET   (0x1)
160
161#define MM_SOFTUSB_PMEM_BASE    (0xa0000000)
162#define MM_SOFTUSB_DMEM_BASE    (0xa0020000)
163
164#define SOFTUSB_PMEM_SIZE       (1 << 13)
165#define SOFTUSB_DMEM_SIZE       (1 << 13)
166
167/* PFPU */
168#define MM_PFPU_CTL             (0xe0006000)
169#define PFPU_CTL_START          (0x01)
170#define PFPU_CTL_BUSY           (0x01)
171
172#define MM_PFPU_MESHBASE        (0xe0006004)
173#define MM_PFPU_HMESHLAST       (0xe0006008)
174#define MM_PFPU_VMESHLAST       (0xe000600C)
175
176#define MM_PFPU_CODEPAGE        (0xe0006010)
177
178#define MM_PFPU_DREGBASE        (0xe0006400)
179#define MM_PFPU_CODEBASE        (0xe0006800)
180
181#define PFPU_PAGESIZE           (512)
182#define PFPU_SPREG_COUNT        (2)
183#define PFPU_REG_X              (0)
184#define PFPU_REG_Y              (1)
185
186/* TMU */
187#define MM_TMU_CTL              (0xe0007000)
188#define TMU_CTL_START           (0x01)
189#define TMU_CTL_BUSY            (0x01)
190#define TMU_CTL_CHROMAKEY       (0x02)
191
192#define MM_TMU_HMESHLAST        (0xe0007004)
193#define MM_TMU_VMESHLAST        (0xe0007008)
194#define MM_TMU_BRIGHTNESS       (0xe000700C)
195#define MM_TMU_CHROMAKEY        (0xe0007010)
196
197#define MM_TMU_VERTICESADR      (0xe0007014)
198#define MM_TMU_TEXFBUF          (0xe0007018)
199#define MM_TMU_TEXHRES          (0xe000701C)
200#define MM_TMU_TEXVRES          (0xe0007020)
201#define MM_TMU_TEXHMASK         (0xe0007024)
202#define MM_TMU_TEXVMASK         (0xe0007028)
203
204#define MM_TMU_DSTFBUF          (0xe000702C)
205#define MM_TMU_DSTHRES          (0xe0007030)
206#define MM_TMU_DSTVRES          (0xe0007034)
207#define MM_TMU_DSTHOFFSET       (0xe0007038)
208#define MM_TMU_DSTVOFFSET       (0xe000703C)
209#define MM_TMU_DSTSQUAREW       (0xe0007040)
210#define MM_TMU_DSTSQUAREH       (0xe0007044)
211
212#define MM_TMU_ALPHA            (0xe0007048)
213
214/* Memory card */
215#define MM_MEMCARD_CLK2XDIV     (0xe0004000)
216
217#define MM_MEMCARD_ENABLE       (0xe0004004)
218
219#define MEMCARD_ENABLE_CMD_TX   (0x1)
220#define MEMCARD_ENABLE_CMD_RX   (0x2)
221#define MEMCARD_ENABLE_DAT_TX   (0x4)
222#define MEMCARD_ENABLE_DAT_RX   (0x8)
223
224#define MM_MEMCARD_PENDING      (0xe0004008)
225
226#define MEMCARD_PENDING_CMD_TX  (0x1)
227#define MEMCARD_PENDING_CMD_RX  (0x2)
228#define MEMCARD_PENDING_DAT_TX  (0x4)
229#define MEMCARD_PENDING_DAT_RX  (0x8)
230
231#define MM_MEMCARD_START        (0xe000400c)
232
233#define MEMCARD_START_CMD_RX    (0x1)
234#define MEMCARD_START_DAT_RX    (0x2)
235
236#define MM_MEMCARD_CMD          (0xe0004010)
237#define MM_MEMCARD_DAT          (0xe0004014)
238
239/* DMX */
240#define MM_DMX_TX(x)            (0xe000c000+4*(x))
241#define MM_DMX_THRU             (0xe000c800)
242#define MM_DMX_RX(x)            (0xe000d000+4*(x))
243
244/* MIDI */
245#define MM_MIDI_RXTX            (0xe000b000)
246#define MM_MIDI_DIV             (0xe000b004)
247#define MM_MIDI_STAT            (0xe000b008)
248#define MM_MIDI_CTRL            (0xe000b00c)
249
250#define MIDI_STAT_THRE          (0x1)
251#define MIDI_STAT_RX_EVT        (0x2)
252#define MIDI_STAT_TX_EVT        (0x4)
253
254#define MIDI_CTRL_RX_INT        (0x1)
255#define MIDI_CTRL_TX_INT        (0x2)
256#define MIDI_CTRL_THRU          (0x4)
257
258/* IR */
259#define MM_IR_RX                (0xe000e000)
260
261/* Video input */
262#define MM_BT656_I2C            (0xe000a000)
263#define MM_BT656_FILTERSTATUS   (0xe000a004)
264#define MM_BT656_BASE           (0xe000a008)
265#define MM_BT656_MAXBURSTS      (0xe000a00c)
266#define MM_BT656_DONEBURSTS     (0xe000a010)
267
268#define BT656_I2C_SDAIN         (0x1)
269#define BT656_I2C_SDAOUT        (0x2)
270#define BT656_I2C_SDAOE         (0x4)
271#define BT656_I2C_SDC           (0x8)
272
273#define BT656_FILTER_FIELD1     (0x1)
274#define BT656_FILTER_FIELD2     (0x2)
275#define BT656_FILTER_INFRAME    (0x4)
276
277/* Interrupts */
278#define MM_IRQ_UART             (0)
279#define MM_IRQ_GPIO             (1)
280#define MM_IRQ_TIMER0           (2)
281#define MM_IRQ_TIMER1           (3)
282#define MM_IRQ_AC97CRREQUEST    (4)
283#define MM_IRQ_AC97CRREPLY      (5)
284#define MM_IRQ_AC97DMAR         (6)
285#define MM_IRQ_AC97DMAW         (7)
286#define MM_IRQ_PFPU             (8)
287#define MM_IRQ_TMU              (9)
288#define MM_IRQ_ETHRX            (10)
289#define MM_IRQ_ETHTX            (11)
290#define MM_IRQ_VIDEOIN          (12)
291#define MM_IRQ_MIDI             (13)
292#define MM_IRQ_IR               (14)
293#define MM_IRQ_USB              (15)
294
295/* Flash layout */
296#define FLASH_BASE                      (0x80000000)
297
298#define FLASH_OFFSET_STANDBY_BITSTREAM  (0x80000000)
299
300#define FLASH_OFFSET_RESCUE_BITSTREAM   (0x800A0000)
301#define FLASH_OFFSET_RESCUE_BIOS        (0x80220000)
302#define FLASH_OFFSET_MAC_ADDRESS        (0x802200E0)
303#define FLASH_OFFSET_RESCUE_SPLASH      (0x80240000)
304#define FLASH_OFFSET_RESCUE_APP         (0x802E0000)
305
306#define FLASH_OFFSET_REGULAR_BITSTREAM  (0x806E0000)
307#define FLASH_OFFSET_REGULAR_BIOS       (0x80860000)
308#define FLASH_OFFSET_REGULAR_SPLASH     (0x80880000)
309#define FLASH_OFFSET_REGULAR_APP        (0x80920000)
310
311/* MMIO */
312#define MM_READ(reg) (*((volatile unsigned int *)(reg)))
313#define MM_WRITE(reg, val) *((volatile unsigned int *)(reg)) = val
314
315/* Flash partitions */
316
317#define FLASH_SECTOR_SIZE     (128*1024)
318
319#define FLASH_PARTITION_COUNT (5)
320
321#define FLASH_PARTITIONS { \
322  { .start_address = 0x806E0000, .length = 0x0180000 }, \
323  { .start_address = 0x80860000, .length = 0x0020000 }, \
324  { .start_address = 0x80880000, .length = 0x00A0000 }, \
325  { .start_address = 0x80920000, .length = 0x0400000 }, \
326  { .start_address = 0x80D20000, .length = 0x12E0000 }, \
327}
328
329#endif /* __SYSTEM_CONFIG_H_ */
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