source: rtems/c/src/lib/libbsp/i960/rxgen960/timer/timerisr.S @ ae7325bd

4.104.114.84.95
Last change on this file since ae7325bd was ae7325bd, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 27, 1999 at 5:25:53 PM

rxgen960 now compiles -- may not link.

  • Property mode set to 100644
File size: 2.0 KB
Line 
1/*  timer_isr()
2 *
3 *  This routine initializes the Z8536 timer on the SQSIO4 SQUALL
4 *  board for the CVME961 board.  The timer is setup to provide a
5 *  tick every 0x10000 / 2 milliseconds.  This is used to time
6 *  executing code.
7 *
8 *  Input parameters:  NONE
9 *
10 *  Output parameters:  NONE
11 *
12 *  COPYRIGHT (c) 1989-1997.
13 *  On-Line Applications Research Corporation (OAR).
14 *  Copyright assigned to U.S. Government, 1994.
15 *
16 *  The license and distribution terms for this file may in
17 *  the file LICENSE in this distribution or at
18 *  http://www.OARcorp.com/rtems/license.html.
19 *
20 *  $Id$
21 */
22
23#include "asm.h"
24
25.set PORT_A,     0xc00000a8                 # port A
26.set PORT_B,     0xc00000a4                 # port B
27.set PORT_C,     0xc00000a0                 # port C
28.set CTL_PORT,   0xc00000ac                 # control port
29
30.set T1CSR,      0x0a                       # T1 command/status reg
31.set RELOAD,     0x24                       # clr IP & IUS,allow countdown
32
33/*
34 * Duplicating this symbol is stupid but eliminates
35 * toolset variation problems.
36 */
37        PUBLIC(timerisr)
38        PUBLIC(_timerisr)
39SYM (timerisr):
40SYM (_timerisr):
41        #ldconst   1,r4
42        #modpc     0,r4,r4               # enable tracing
43
44        ld      _Ttimer_val,r6           # r6 = test timer
45
46        ldconst T1CSR,r4                 # r4 = T1 control status reg
47        stob    r4,CTL_PORT              # select T1CSR
48        ldconst RELOAD,r5                # r5 = reset value
49        stob    r5,CTL_PORT              # reset countdown
50        addo    1,r6,r6
51        st      r6,_Ttimer_val           # increment test timer
52loop_til_cleared:
53        /* clrbit 4,sf0,sf0 XXX JRS */
54        /* bbs    4,sf0,loop_til_cleared XXX JRS */
55leaf:   ret
56
57        .leafproc _flush_reg, flush_reg.lf
58        .globl    _flush_reg, flush_reg.lf
59_flush_reg:
60        lda     leaf,g14                 # g14 = exit address
61flush_reg.lf:
62        flushreg
63        mov     g14,g0                   # g0 = exit address
64        ldconst 0,g14                    # set g14 for non-leaf
65        bx      (g0)
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