source: rtems/c/src/lib/libbsp/i960/rxgen960/startup/prcb.c @ 8ac4213

4.104.114.84.95
Last change on this file since 8ac4213 was 702c5f5, checked in by Joel Sherrill <joel.sherrill@…>, on 10/27/99 at 15:29:18

The rxgen960 BSP and i960 RPM support was submitted by Mark Bronson
<mark@…> of RAMIX.

  • Property mode set to 100644
File size: 1.7 KB
Line 
1/*-------------------------------------*/
2/* prcb.c                              */
3/* Last change : 11.10.94              */
4/*-------------------------------------*/
5#include "flttbl.h"
6#include "cntrltbl.h"
7#include "intrtbl.h"
8#include "systbl.h"
9#include "prcb.h"
10/*-------------------------------------*/
11  /* RAM based PRocess Control Block 
12   */     
13#ifdef DBPRECISE_FAULTS
14#define AC                      (INT_OVFL_DISABLE | PRECISE_FLTS)
15#else
16#define AC                      (INT_OVFL_DISABLE | IMPRECISE_FLTS)
17#endif
18
19 /* Initial Fault Configuration Word Image.
20   * As to this 1, I don't know why but without it
21   * fault hanlder wouldn't be invoked.
22   */
23#define FAULT_CONFIG            (UNLGND_FAULT_DISABLE | 1)
24
25  /* Initial Instruction Cache Configuration Word Image.
26   */
27#ifdef DBCACHE_OFF
28#define INST_CACHE_CONFIG       (INST_CACHE_DISABLE)
29#else
30#define INST_CACHE_CONFIG       (INST_CACHE_ENABLE)
31#endif
32
33  /* Initial Register Cache Configuration Word Image.
34   */
35#define REG_CACHE_CONFIG        0x000
36
37
38struct PRCB ram_prcb = {
39  & faultTbl[0],                        /* Fault Table Base */   
40  & controlTbl[0],                  /* Control Table Base */   
41  AC,                                   /* AC */
42  FAULT_CONFIG,                         /* Fault Configuration Word */
43  & interruptTbl,                       /* Interrupt Table Base */
44  & systemTbl,                          /* System Procedure Table Base */   
45  0,                                    /* Reserved */ 
46  & intStackPtr[0],                     /* Interrupt Stack Pointer */
47  INST_CACHE_CONFIG,                    /* Instruction Cache Config */
48  REG_CACHE_CONFIG,                     /* Reg Cache Config */
49}; 
50
51/*-------------*/
52/* End of file */
53/*-------------*/
54
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