source: rtems/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.h @ 702c5f5

4.104.114.84.95
Last change on this file since 702c5f5 was 702c5f5, checked in by Joel Sherrill <joel.sherrill@…>, on 10/27/99 at 15:29:18

The rxgen960 BSP and i960 RPM support was submitted by Mark Bronson
<mark@…> of RAMIX.
  • Property mode set to 100644
File size: 916 bytes
Line 
1/*-------------------------------------*/
2/* cntrltbl.h                          */
3/* Last change : 11. 1.95              */
4/*-------------------------------------*/
5#ifndef _CNTRLTBL_H_
6#define _CNTRLTBL_H_
7
8  /* Control Table Entry.   
9   */
10typedef unsigned int ControlTblEntry;
11  /* Control Table itself.
12   */
13extern ControlTblEntry controlTbl[];
14extern ControlTblEntry rom_controlTbl[];
15
16  /* Interrupt Registers Initial.
17   */     
18#define IPB0            0
19#define IPB1            0
20#define DAB0            0 
21#define DAB1            0 
22
23#define I_DISABLE       (0x1<<10)
24#define I_ENABLE        0
25
26#define MSK_UNCHNG      0
27#define MSK_CLEAR  (0x1<<11)
28
29#define VECTOR_CACHE    (0x1<<13)
30
31
32
33  /* BreakPoint Control Register Initial.
34   */
35#define BPCON           0 
36  /* Bus Controller Mode Comstants.
37  */
38#define CONF_TBL_VALID  0x1
39#define PROTECT_RAM     0x2 
40#define PROTECT_RAM_SUP 0x4
41
42
43
44#endif   
45/*-------------*/
46/* End of file */
47/*-------------*/
48
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