[ac7d5ef0] | 1 | /* set_vector |
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| 2 | * |
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| 3 | * This routine attempts to perform all "generic" interrupt initialization |
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| 4 | * for the specified XINT line. It is specific to the Cyclone CVME961 in |
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| 5 | * that it knows which interrupts are initialized by the monitor, the |
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| 6 | * characteristics of XINT5 (VIC068 clock tick), and that it assumes the |
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| 7 | * i960 is processing interrupts in dedicated mode. It attempts to map |
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| 8 | * XINTs to interrupt vectors in a fairly straght forward way. |
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| 9 | * |
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| 10 | * XINT USE VECTOR INTR TBL INDEX TRIGGERED |
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| 11 | * ==== ============= ====== ============== ========= |
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| 12 | * 0 VMEbus ERROR 0x02 0x03 EDGE |
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| 13 | * 1 DRAM PARITY 0x12 0x13 EDGE |
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| 14 | * 2 Z8530 0x22 0x23 LEVEL |
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| 15 | * 3 SQUALL 0 0x52 0x53 ---- |
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| 16 | * 4 Z8536 (SQSIO4) 0x72 0x73 LEVEL |
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| 17 | * 5 TICK 0x32 0x33 EDGE |
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| 18 | * 6 VIC068 0x62 0x63 LEVEL |
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| 19 | * 7 UNUSED 0x42 0x43 LEVEL |
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| 20 | * |
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| 21 | * The interrupt handler is installed in both the cached and memory |
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| 22 | * resident interrupt tables. The appropriate IMAP register is updated to |
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| 23 | * reflect the vector selected by this routine. Global interrupts are |
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| 24 | * enabled. If XINT5 is being installed, places it in trigger mode. |
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| 25 | * Finally, set_vector_support() is invoked to install the new IMAP and |
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| 26 | * ICON, unmask the XINT in IMASK, and lower the i960's interrupt |
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| 27 | * level to 0. |
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| 28 | * |
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| 29 | * INPUT: |
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| 30 | * func - interrupt handler entry point |
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| 31 | * xint - external interrupt line |
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| 32 | * type - 0 indicates raw hardware connect |
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| 33 | * 1 indicates RTEMS interrupt connect |
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| 34 | * |
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| 35 | * RETURNS: |
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| 36 | * address of previous interrupt handler |
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| 37 | * |
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| 38 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 39 | * On-Line Applications Research Corporation (OAR). |
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| 40 | * All rights assigned to U.S. Government, 1994. |
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| 41 | * |
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| 42 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 43 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 44 | * notice must appear in all copies of this file and its derivatives. |
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| 45 | * |
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| 46 | * $Id$ |
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| 47 | */ |
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| 48 | |
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| 49 | #include <rtems.h> |
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| 50 | #include <bsp.h> |
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| 51 | |
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| 52 | #include <stdio.h> |
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| 53 | |
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| 54 | void print_prcb(); |
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| 55 | void print_intr_info(); |
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| 56 | void print_ipnd_imsk(); |
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| 57 | |
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| 58 | unsigned int Xint_2_Group_Map[8] = { 0, 1, 2, 5, 7, 3, 6, 4 }; |
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| 59 | |
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[e8512eb] | 60 | i960_isr_entry set_vector( /* returns old vector */ |
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[ac7d5ef0] | 61 | rtems_isr_entry func, /* isr routine */ |
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| 62 | unsigned int xint, /* XINT number */ |
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| 63 | unsigned int type /* RTEMS or RAW */ |
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| 64 | ) |
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| 65 | { |
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[e8512eb] | 66 | i960_isr_entry *intr_tbl, *cached_intr_tbl; |
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| 67 | i960_isr_entry saved_intr; |
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[ac7d5ef0] | 68 | unsigned int vector, group, nibble; |
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| 69 | unsigned int *imap; |
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| 70 | |
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| 71 | if ( xint > 7 ) |
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| 72 | exit( 0x80 ); |
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| 73 | |
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[e8512eb] | 74 | cached_intr_tbl = (i960_isr_entry *) 0; |
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| 75 | intr_tbl = (i960_isr_entry *) Prcb->intr_tbl; |
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[ac7d5ef0] | 76 | group = Xint_2_Group_Map[xint]; /* remap XINT to group */ |
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| 77 | vector = (group << 4) + 2; /* direct vector num */ |
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| 78 | |
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| 79 | if ( type ) |
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| 80 | rtems_interrupt_catch( func, vector, (rtems_isr_entry *) &saved_intr ); |
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| 81 | else { |
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[e8512eb] | 82 | saved_intr = (i960_isr_entry) intr_tbl[ vector ]; |
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| 83 | /* return old vector */ |
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| 84 | intr_tbl[ vector + 1 ] = /* normal vector table */ |
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| 85 | cached_intr_tbl[ group ] = (i960_isr_entry) func; /* cached vector */ |
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[ac7d5ef0] | 86 | } |
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| 87 | |
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| 88 | if ( xint <= 3 ) imap = &Ctl_tbl->imap0; /* updating IMAP0 */ |
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| 89 | else imap = &Ctl_tbl->imap1; /* updating IMAP1 */ |
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| 90 | nibble = (xint % 4) * 4; |
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| 91 | *imap &= ~(0xf << nibble); |
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| 92 | *imap |= group << nibble; |
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| 93 | |
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| 94 | Ctl_tbl->icon &= ~0x00000400; /* enable global interrupts */ |
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| 95 | Ctl_tbl->icon |= 0x00004000; /* fast sampling mode */ |
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| 96 | switch ( xint ) { |
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| 97 | case 0: Ctl_tbl->icon |= 0x00000004; break; |
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| 98 | case 1: Ctl_tbl->icon |= 0x00000008; break; |
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| 99 | case 2: Ctl_tbl->icon &= ~0x00000010; break; |
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| 100 | case 4: Ctl_tbl->icon &= ~0x00000040; break; |
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| 101 | case 5: Ctl_tbl->icon |= 0x00000080; break; |
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| 102 | case 6: Ctl_tbl->icon &= ~0x00000100; break; |
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| 103 | default: exit( 0x81 ); break; /* unsupported */ |
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| 104 | } |
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| 105 | |
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| 106 | if ( xint == 4 ) { /* reprogram MCON for SQSIO4 */ |
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| 107 | Ctl_tbl->mcon12 = 0x00002012; /* MCON12 - 0xCxxxxxxx */ |
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| 108 | Ctl_tbl->mcon13 = 0x00000000; /* MCON13 - 0xDxxxxxxx */ |
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| 109 | i960_reload_ctl_group( 5 ); /* update MCON12-MCON15 */ |
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| 110 | } |
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| 111 | |
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| 112 | i960_unmask_intr( xint ); /* update IMSK */ |
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| 113 | i960_reload_ctl_group( 1 ); /* update IMAP?/ICON */ |
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| 114 | return( saved_intr ); /* return old vector */ |
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| 115 | } |
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| 116 | |
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| 117 | void print_prcb() |
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| 118 | { |
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| 119 | printf( "fault_table =0x%p\n", Prcb->fault_tbl ); |
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| 120 | printf( "control_tbl =0x%p\n", Prcb->control_tbl ); |
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| 121 | printf( "AC mask ov =0x%x\n", Prcb->initial_ac ); |
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| 122 | printf( "fltconfig =0x%x\n", Prcb->fault_config ); |
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| 123 | printf( "intr tbl =0x%p\n", Prcb->intr_tbl ); |
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| 124 | printf( "systable =0x%p\n", Prcb->sys_proc_tbl ); |
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| 125 | printf( "reserved =0x%x\n", Prcb->reserved ); |
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| 126 | printf( "isr stk =0x%p\n", Prcb->intr_stack ); |
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| 127 | printf( "ins cache =0x%x\n", Prcb->ins_cache_cfg ); |
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| 128 | printf( "reg cache =0x%x\n", Prcb->reg_cache_cfg ); |
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| 129 | } |
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| 130 | |
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| 131 | void print_intr_info() |
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| 132 | { |
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| 133 | printf( "prcb =0x%p\n", Prcb ); |
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| 134 | printf( "ctl_tbl =0x%p\n", Ctl_tbl ); |
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| 135 | printf( "intr_tbl=0x%p\n", Prcb->intr_tbl ); |
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| 136 | printf( "IMAP0 = 0x%x\n", Ctl_tbl->imap0 ); |
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| 137 | printf( "IMAP1 = 0x%x\n", Ctl_tbl->imap1 ); |
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| 138 | print_ipnd_imsk(); |
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| 139 | } |
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| 140 | |
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| 141 | void print_ipnd_imsk() |
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| 142 | { |
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| 143 | printf(" IPEND = 0x%x\n", i960_pend_intrs() ); |
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| 144 | printf(" IMASK = 0x%x\n", i960_mask_intrs() ); |
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| 145 | } |
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