1 | /* |
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2 | * This file is the main boot and configuration file for the TS-1325. It is |
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3 | * solely responsible for initializing the internal register set to reflect |
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4 | * the proper board configuration. This version is modified from the i386ex |
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5 | * BSP startup: |
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6 | * |
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7 | * 1) 1 MB RAM @ 0x0100000 |
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8 | * 2) 1 MB RAM @ 0x0 but with standard DOS memory usage. |
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9 | * 3) Timer0 used as RTEMS clock ticker, 1 msec tick rate. |
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10 | * 4) READY# is generated by CPU |
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11 | * |
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12 | * The file describes the ".initial" section, which contains: |
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13 | * 1) device configuration code |
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14 | * 2) interrupt descriptor table |
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15 | * 3) global descriptor table |
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16 | * 4) and initial boot code |
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17 | * |
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18 | * Modified by: |
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19 | * |
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20 | * Tony Ambardar |
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21 | * University of British Columbia |
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22 | * tonya@ece.ubc.ca |
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23 | * |
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24 | * The license and distribution terms for this file may be |
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25 | * found in the file LICENSE in this distribution or at |
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26 | * http://www.rtems.com/license/LICENSE. |
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27 | * |
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28 | * $Id$ |
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29 | */ |
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30 | |
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31 | #include <rtems/asm.h> |
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32 | #include "macros.inc" |
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33 | #include "80386ex.inc" |
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34 | |
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35 | #include "ts_1325.inc" /* controls for LED and button */ |
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36 | |
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37 | /* |
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38 | * NEW_GAS Needed for binutils 2.9.1.0.7 and higher |
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39 | */ |
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40 | |
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41 | EXTERN (boot_card) /* exits to bspstart */ |
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42 | EXTERN (_DOS_seg_base) /* defined in startup/linkcmds */ |
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43 | EXTERN (Clock_exit) |
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44 | |
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45 | PUBLIC (Interrupt_descriptor_table) |
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46 | PUBLIC ( SYM(IDTR) ) |
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47 | PUBLIC (_Global_descriptor_table) |
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48 | PUBLIC ( SYM(GDTR) ) |
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49 | |
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50 | PUBLIC( SYM(_init_i386ex) ) |
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51 | |
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52 | .section .initial, "ax" |
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53 | |
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54 | /* |
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55 | * Enable access to peripheral register at expanded I/O addresses |
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56 | */ |
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57 | SYM(_init_i386ex): |
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58 | .code16 |
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59 | /* |
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60 | LED_GREEN |
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61 | WAIT_BUTTON |
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62 | */ |
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63 | # cli Move this up for now for debug. |
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64 | movw $0x8000 , ax |
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65 | outb al , $REMAPCFGH |
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66 | xchg al , ah |
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67 | outb al , $REMAPCFGL |
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68 | outw ax , $REMAPCFG ; |
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69 | /* |
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70 | LED_OFF |
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71 | WAIT_BUTTON |
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72 | */ |
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73 | /* |
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74 | * Configure operation of the A20 Address Line |
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75 | */ |
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76 | SYM(A20): |
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77 | movw $PORT92 , dx |
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78 | |
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79 | inb dx , al # clear A20 port reset |
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80 | andb $0xfe , al # b0 Fast Reset(0)=disabled,(1)=reset triggered |
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81 | orb $0x02 , al # Bit 1 Fast A20 = 0 (always 0) else enabled. |
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82 | outb al , dx |
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83 | /* |
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84 | LED_YELLOW |
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85 | WAIT_BUTTON |
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86 | */ |
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87 | SYM(Watchdog): |
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88 | movw $WDTSTATUS , dx # address the WDT status port |
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89 | inb dx , al # get the WDT status |
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90 | orb $0x01 , al # set the CLKDIS bit |
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91 | outb al , dx # disable the clock to the WDT |
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92 | /* |
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93 | LED_GREEN |
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94 | WAIT_BUTTON |
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95 | */ |
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96 | /* |
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97 | * Initialize Refresh Control Unit for: |
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98 | * Refresh Address = 0x0000 |
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99 | |
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100 | * Refresh gate between rows is 20.0 (???) uSec |
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101 | * Using a CLK2 frequency of 50Mhz ( 25Mhz CPU ) |
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102 | * The refresh unit is enabled |
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103 | * The refresh pin is not used. |
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104 | * |
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105 | * Different TS units might have different refresh intervals, so |
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106 | * comment out. Will be set up anyway after booting to DOS. |
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107 | */ |
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108 | |
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109 | /* |
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110 | SYM(InitRCU): |
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111 | SetExRegWord( RFSCIR , 0x1F4) # refresh interval 500 |
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112 | SetExRegWord( RFSBAD , 0x0) # base address |
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113 | SetExRegWord( RFSADD , 0x0) # address register |
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114 | SetExRegWord( RFSCON , 0x8000) # enable bit |
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115 | */ |
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116 | |
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117 | /* |
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118 | LED_OFF |
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119 | WAIT_BUTTON |
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120 | */ |
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121 | /* |
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122 | * Initialize clock and power mgmt unit for: |
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123 | * Clock Frequency = 50 Mhz |
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124 | * Prescaled clock output = 1 Mhz |
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125 | * Normal halt instructions |
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126 | * |
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127 | * NOTE: Hope this doesn't change the COMCLK frequency |
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128 | */ |
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129 | |
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130 | SYM(InitClk): |
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131 | SetExRegByte( PWRCON, 0x0 ) |
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132 | SetExRegWord( CLKPRS, 0x17) # 0x13 for 1.19318 MHz. 0x17 for 1MHz. |
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133 | |
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134 | /************************************************************** |
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135 | * Initialize the Pin Configurations |
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136 | *************************************************************/ |
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137 | /* |
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138 | LED_YELLOW |
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139 | WAIT_BUTTON |
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140 | */ |
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141 | /* |
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142 | * Initialize I/O port 1 for: |
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143 | * PIN 0 = 0, Inport for external push-button switch |
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144 | * PIN 1 = 1, RTS0# to package pin |
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145 | * PIN 2 = 1, DTR0# to package pin |
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146 | * PIN 3 = 1, DSR0# to package pin |
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147 | * PIN 4 = 0, Inport ??? |
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148 | * PIN 5 = 0, Outport (Green LED, 1 = ON) |
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149 | * PIN 6 = 0, Outport (Red LED, 1 = OFF) |
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150 | * PIN 7 = 0, Inport ??? |
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151 | */ |
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152 | |
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153 | SYM(InitPort1): |
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154 | SetExRegByte( P1LTC , 0xd1 ) |
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155 | SetExRegByte( P1DIR , 0x91) |
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156 | SetExRegByte( P1CFG , 0x0e) |
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157 | /* |
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158 | LED_GREEN |
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159 | WAIT_BUTTON |
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160 | */ |
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161 | /* |
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162 | * Initialize I/O port 2 for: |
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163 | * PIN 0 = 0, Outport ??? |
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164 | * PIN 1 = 0, Outport ??? |
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165 | * PIN 2 = 0, Outport ??? |
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166 | * PIN 3 = 0, Outport ??? |
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167 | * PIN 4 = 0, Outport ??? |
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168 | * PIN 5 = 1, Int. periph, RXD0 |
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169 | * PIN 6 = 1, Int. periph, TXD0 |
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170 | * PIN 7 = 0, Outport ??? |
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171 | */ |
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172 | |
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173 | SYM(InitPort2): |
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174 | SetExRegByte( P2LTC , 0x1f ) |
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175 | SetExRegByte( P2DIR , 0x00 ) |
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176 | SetExRegByte( P2CFG , 0x60) |
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177 | /* |
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178 | LED_OFF |
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179 | WAIT_BUTTON |
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180 | */ |
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181 | /* |
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182 | * Initialize I/O port 3 P3CFG |
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183 | * PIN 0 = 1, Int. periph, TMROUT0 |
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184 | * PIN 1 = 1, Int. periph, TMROUT1 |
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185 | * PIN 2 = 1, Int. periph, INT0 (IR1) |
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186 | * PIN 3 = 1, Int. periph, INT1 (IR5) |
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187 | * PIN 4 = 1, Int. periph, INT2 (IR6) |
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188 | * PIN 5 = 1, Int. periph, INT2 (IR7) |
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189 | * PIN 6 = 0, Outport ??? |
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190 | * PIN 7 = 1, Int. periph, COMCLK used for serial I/O |
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191 | */ |
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192 | |
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193 | SYM(InitPort3): |
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194 | SetExRegByte( P3LTC , 0x00 ) |
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195 | SetExRegByte( P3DIR , 0xbf ) |
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196 | SetExRegByte( P3CFG , 0xbf ) # can check TMROUT0 |
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197 | /* |
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198 | LED_YELLOW |
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199 | WAIT_BUTTON |
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200 | */ |
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201 | /* |
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202 | * Initialize Peripheral Pin Configurations: |
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203 | * PIN 0 = 1, Select RTS1# |
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204 | * PIN 1 = 1, Select DTR1# |
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205 | * PIN 2 = 1, Select TXD1# |
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206 | * PIN 3 = 1, Select CTS1# |
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207 | * PIN 4 = 1, CS5 |
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208 | * PIN 5 = 1, Timer2 pins enabled |
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209 | * PIN 6 = 0, Select CS6# |
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210 | * PIN 7 = 0, Don't care |
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211 | */ |
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212 | |
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213 | SYM(InitPeriph): |
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214 | SetExRegByte( PINCFG , 0x3f) |
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215 | /* |
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216 | LED_GREEN |
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217 | WAIT_BUTTON |
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218 | */ |
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219 | /* |
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220 | * Initialize the Asynchronous Serial Ports: |
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221 | * BIT 7 = 1, Internal SIO1 modem signals |
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222 | * BIT 6 = 1, Internal SIO0 modem signals |
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223 | * BIT 2 = 0, PSCLK for SSIO clock |
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224 | * BIT 1 = 1, SERCLK for SIO1 clock |
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225 | * BIT 0 = 1, SERCLK for SIO0 clock |
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226 | */ |
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227 | |
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228 | SYM(InitSIO): |
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229 | SetExRegByte( SIOCFG, 0x00 ) # COMCLK -> baud-rate generator |
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230 | # modem signals -> package pins |
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231 | SetExRegByte( LCR0, 0x80 ) # latch DLL0, DLH0 |
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232 | SetExRegByte( DLL0, 0x01 ) # 0x0C sets to 9600 baud 0x6 = 19.2K |
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233 | SetExRegByte( DLH0, 0x00 ) # 0x4 is 28.8K baud, 0x1 is 115K baud |
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234 | SetExRegByte( LCR0, 0x03 ) # enable r/w buffers, IER0 accessible |
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235 | # mode 8-n-1 |
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236 | SetExRegByte( IER0, 0x00 ) # no generated interrupts |
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237 | |
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238 | SetExRegByte( LCR1, 0x80 ) # latch DLL0, DLH0 |
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239 | SetExRegByte( DLL1, 0x01 ) # 0x0C set to 9600 baud, 0x6 = 19.2K |
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240 | SetExRegByte( DLH1, 0x00 ) # 0x4 is 28.8K baud |
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241 | SetExRegByte( LCR1, 0x03 ) # enable r/w buffers, IER1 accessible |
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242 | # reg 8-n-1 |
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243 | SetExRegByte( IER1, 0x00 ) # no generated intrrupts |
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244 | /* |
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245 | LED_OFF |
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246 | WAIT_BUTTON |
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247 | */ |
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248 | SYM(InitMCR): |
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249 | SetExRegByte( MCR0, 0x03 ) # standard mode, RTS,DTR activated |
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250 | SetExRegByte( MCR1, 0x03 ) # standard mode, RTS,DTR activated |
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251 | |
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252 | /* |
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253 | * Initialize Timer for: |
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254 | * BIT 7 = 1, Timer clocks disabled |
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255 | * BIT 6 = 0, Reserved |
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256 | * BIT 5 = 1, TMRCLK2 instead of Vcc to Gate2 |
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257 | * BIT 4 = 0, PSCLK to CLK2 |
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258 | * BIT 3 = 1, TMRCLK1 instead of Vcc to Gate1 |
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259 | * BIT 2 = 0, PSCLK to Gate1 |
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260 | * BIT 1 = 0, Vcc to Gate0 |
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261 | * BIT 0 = 0, PSCLK to Gate0 |
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262 | */ |
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263 | /* |
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264 | LED_YELLOW |
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265 | WAIT_BUTTON |
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266 | */ |
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267 | SYM(InitTimer): |
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268 | SetExRegByte(TMRCFG , 0x80 ) # All counters disabled, Gates 0,1 |
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269 | # and 2 are set to Vcc |
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270 | |
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271 | SetExRegByte(TMRCON , 0x34 ) # prepare to write counter 0 LSB,MSB |
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272 | SetExRegByte(TMR0 , 0x00 ) # sfa |
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273 | SetExRegByte(TMR0 , 0x00 ) # sfa |
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274 | |
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275 | SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc |
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276 | SetExRegByte(TMR1 , 0x00 ) # sfa |
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277 | SetExRegByte(TMR1 , 0x00 ) # sfa |
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278 | |
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279 | SetExRegByte(TMRCON , 0xB0 ) # mode 0 disables on gate =Vcc |
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280 | SetExRegByte(TMR2 , 0x00 ) # |
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281 | SetExRegByte(TMR2 , 0x00 ) # |
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282 | |
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283 | /* |
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284 | LED_GREEN |
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285 | WAIT_BUTTON |
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286 | */ |
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287 | /* |
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288 | * Initialize the DMACFG register for: |
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289 | * BIT 7 = 1 , Disable DACK#1 |
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290 | * BITs 6:4 = 100, TMROUT2 connected to DRQ1 |
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291 | * BIT 3 = 1 , Disable DACK0# |
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292 | * BIT 2:0 = 000, Pin is connected to DRQ0 |
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293 | * |
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294 | * NOTE: not 100% sure of this... |
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295 | */ |
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296 | |
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297 | SetExRegByte(DMACFG , 0xC0 ) |
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298 | SetExRegByte(DMACMD1, 0x00 ) # disable both DMA channels |
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299 | SetExRegByte(DMAMOD1, 0x40 ) # DMA0 single transer mode |
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300 | /* |
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301 | LED_OFF |
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302 | WAIT_BUTTON |
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303 | */ |
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304 | /* |
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305 | * Initialize the INTCFG register for: |
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306 | * BIT 7 = 0, 8259 cascade disabled |
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307 | * BIT 3 = 0, SLAVE IR6 connected to Vss |
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308 | * BIT 2 = 0, SLAVE IR5 connected to Vss |
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309 | * BIT 1 = 0, SLAVE IR1 connected to SSIOINT |
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310 | * BIT 0 = 0, SLAVE IR0 connected to Vss |
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311 | * |
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312 | * NOTE: not 100% sure of this either... Why IR5 active? |
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313 | */ |
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314 | |
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315 | SYM(InitInt): |
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316 | |
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317 | cli # ! |
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318 | /* |
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319 | LED_YELLOW |
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320 | WAIT_BUTTON |
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321 | */ |
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322 | SetExRegByte(ICW1S , 0x11 ) # EDGE TRIGGERED |
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323 | SetExRegByte(ICW2S , 0x28 ) # Slave base vector after Master |
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324 | SetExRegByte(ICW3S , 0x02 ) # slave cascaded to IR2 on master |
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325 | SetExRegByte(ICW4S , 0x01 ) # fully nested mode, no EOI |
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326 | |
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327 | SetExRegByte(ICW1M , 0x11 ) # edge triggered |
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328 | SetExRegByte(ICW2M , 0x20 ) # base vector starts at byte 32 |
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329 | SetExRegByte(ICW3M , 0x04) # internal slave cascaded from master IR2 |
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330 | SetExRegByte(ICW4M , 0x01 ) # idem |
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331 | |
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332 | SetExRegByte(OCW1M , 0xfb ) # mask master IRQs, but not IR2 (cascade) |
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333 | SetExRegByte(OCW1S , 0xff ) # mask all slave IRQs |
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334 | SetExRegByte(INTCFG , 0x00 ) # slave IRs -> Vss or SSIOINT |
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335 | |
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336 | /* The i8259s_cache (IRQ mask) location is in BSS, which is zeroed later! |
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337 | * So to initialize the cache we should do the following command after |
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338 | * the BSS is zeroed, and in 32-bit protected mode. |
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339 | * |
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340 | * movw $0xFFFB, SYM(i8259s_cache) |
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341 | * |
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342 | */ |
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343 | |
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344 | /* |
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345 | NOTE: not sure about this so comment out... |
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346 | |
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347 | SYM(SetCS4): |
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348 | SetExRegWord(CS4ADL , 0x702) #Configure chip select 4 |
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349 | SetExRegWord(CS4ADH , 0x00) |
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350 | SetExRegWord(CS4MSKH, 0x03F) |
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351 | SetExRegWord(CS4MSKL, 0xFC01) |
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352 | */ |
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353 | /* |
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354 | LED_GREEN |
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355 | WAIT_BUTTON |
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356 | */ |
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357 | /***************************** |
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358 | * Load the Global Descriptor |
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359 | * Table Register |
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360 | ****************************/ |
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361 | |
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362 | movl $SYM(GDTR), eax |
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363 | andl $0xFFFF, eax |
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364 | |
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365 | #ifdef NEW_GAS |
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366 | addr32 |
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367 | data32 |
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368 | #endif |
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369 | |
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370 | #if 0 |
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371 | lgdt (eax) # location of GDT in segment |
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372 | #endif |
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373 | lgdt SYM(GDTR) # location of GDT |
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374 | |
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375 | /* |
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376 | NOTE: not sure about this either so comment out for now... |
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377 | SYM(SetUCS): |
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378 | SetExRegWord(UCSADL, 0xC503) # values taken from TS-1325 memory |
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379 | SetExRegWord(UCSADH, 0x000D) |
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380 | SetExRegWord(UCSMSKH, 0x0000) |
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381 | SetExRegWord(UCSMSKL, 0x3C01) # configure upper chip select |
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382 | */ |
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383 | /* |
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384 | LED_OFF |
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385 | WAIT_BUTTON |
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386 | */ |
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387 | /*************************** |
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388 | * Switch to Protected Mode |
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389 | ***************************/ |
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390 | mov cr0, eax |
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391 | orw $0x1, ax |
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392 | mov eax, cr0 |
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393 | |
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394 | /************************** |
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395 | * Flush prefetch queue, |
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396 | * and load CS selector |
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397 | *********************/ |
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398 | /* |
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399 | LED_YELLOW |
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400 | WAIT_BUTTON |
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401 | */ |
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402 | ljmpl $ GDT_CODE_PTR , $ SYM(_load_segment_registers) # sets the code selector |
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403 | |
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404 | /* |
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405 | * Load the segment registers |
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406 | */ |
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407 | SYM(_load_segment_registers): |
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408 | .code32 |
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409 | /* |
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410 | LED_GREEN |
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411 | WAIT_BUTTON |
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412 | */ |
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413 | pLOAD_SEGMENT( GDT_DATA_PTR, fs) |
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414 | pLOAD_SEGMENT( GDT_DATA_PTR, gs) |
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415 | pLOAD_SEGMENT( GDT_DATA_PTR, ss) |
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416 | pLOAD_SEGMENT( GDT_DATA_PTR, ds) |
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417 | pLOAD_SEGMENT( GDT_DATA_PTR, es) |
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418 | |
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419 | /* |
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420 | * Set up the stack |
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421 | */ |
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422 | /* |
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423 | LED_OFF |
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424 | WAIT_BUTTON |
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425 | */ |
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426 | SYM(lidtr): |
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427 | lidt SYM(IDTR) |
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428 | /* |
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429 | LED_YELLOW |
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430 | WAIT_BUTTON |
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431 | */ |
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432 | SYM (_establish_stack): |
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433 | movl $_ebss, eax # stack starts right after bss |
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434 | movl $stack_origin, esp # this is the high starting address |
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435 | movl $stack_origin, ebp |
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436 | /* |
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437 | LED_GREEN |
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438 | WAIT_BUTTON |
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439 | */ |
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440 | /* |
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441 | * Zero out the BSS segment |
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442 | */ |
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443 | SYM (zero_bss): |
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444 | cld # make direction flag count up |
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445 | movl $ SYM (_ebss),ecx # find end of .bss |
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446 | movl $ SYM (_bss_start),edi # edi = beginning of .bss |
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447 | subl edi,ecx # ecx = size of .bss in bytes |
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448 | shrl ecx # size of .bss in longs |
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449 | shrl ecx |
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450 | xorl eax,eax # value to clear out memory |
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451 | repne # while ecx != 0 |
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452 | stosl # clear a long in the bss |
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453 | /* |
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454 | * Now we can initialize the IRQ mask in i8259s_cache |
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455 | */ |
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456 | movw $0xFFFB, SYM(i8259s_cache) |
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457 | /* |
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458 | LED_YELLOW # Indicate ready to run |
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459 | WAIT_BUTTON |
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460 | */ |
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461 | LED_GREEN # Indicate RTEMS running! |
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462 | |
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463 | /* |
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464 | * Transfer control to User's Board Support Package |
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465 | */ |
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466 | pushl $0 # environp |
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467 | pushl $0 # argv |
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468 | pushl $0 # argc |
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469 | call SYM(boot_card) |
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470 | addl $12,esp |
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471 | |
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472 | LED_RED # Indicate RTEMS exited |
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473 | /* |
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474 | WAIT_BUTTON |
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475 | */ |
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476 | cli # stops interrupts after hlt! |
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477 | hlt # shutdown |
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478 | |
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479 | .balign 4 # align tables to 4 byte boundary |
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480 | |
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481 | SYM(IDTR): DESC3( SYM(Interrupt_descriptor_table), 0x07ff ); |
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482 | |
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483 | SYM(Interrupt_descriptor_table): /* Now in data section */ |
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484 | .rept 256 |
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485 | .word 0,0,0,0 |
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486 | .endr |
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487 | |
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488 | /* |
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489 | * Use the first (null) entry in the the GDT as a self-pointer for the GDTR. |
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490 | * (looks like a common trick) |
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491 | */ |
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492 | |
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493 | SYM (_Global_descriptor_table): |
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494 | SYM(GDTR): DESC3( GDTR, 0x17 ); # one less than the size |
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495 | .word 0 # padding to DESC2 size |
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496 | SYM(GDT_CODE): DESC2(0xffff,0,0x0,0x9B,0xDF,0x00); |
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497 | SYM(GDT_DATA): DESC2(0xffff,0,0x0,0x92,0xDF,0x00); # was CF |
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498 | SYM(GDT_END): |
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499 | |
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500 | END |
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