1 | |
---|
2 | /* Register descriptions */ |
---|
3 | /* Controller DP8390. */ |
---|
4 | |
---|
5 | #define DATAPORT 0x10 /* Port Window. */ |
---|
6 | #define RESET 0x1f /* Issue a read for reset */ |
---|
7 | #define W83CREG 0x00 /* I/O port definition */ |
---|
8 | #define ADDROM 0x08 |
---|
9 | |
---|
10 | /* page 0 read or read/write registers */ |
---|
11 | |
---|
12 | #define CMDR 0x00+RO |
---|
13 | #define CLDA0 0x01+RO /* current local dma addr 0 for read */ |
---|
14 | #define CLDA1 0x02+RO /* current local dma addr 1 for read */ |
---|
15 | #define BNRY 0x03+RO /* boundary reg for rd and wr */ |
---|
16 | #define TSR 0x04+RO /* tx status reg for rd */ |
---|
17 | #define NCR 0x05+RO /* number of collision reg for rd */ |
---|
18 | #define FIFO 0x06+RO /* FIFO for rd */ |
---|
19 | #define ISR 0x07+RO /* interrupt status reg for rd and wr */ |
---|
20 | #define CRDA0 0x08+RO /* current remote dma address 0 for rd */ |
---|
21 | #define CRDA1 0x09+RO /* current remote dma address 1 for rd */ |
---|
22 | #define RSR 0x0C+RO /* rx status reg for rd */ |
---|
23 | #define CNTR0 0x0D+RO /* tally cnt 0 for frm alg err for rd */ |
---|
24 | #define CNTR1 RO+0x0E /* tally cnt 1 for crc err for rd */ |
---|
25 | #define CNTR2 0x0F+RO /* tally cnt 2 for missed pkt for rd */ |
---|
26 | |
---|
27 | /* page 0 write registers */ |
---|
28 | |
---|
29 | #define PSTART 0x01+RO /* page start register */ |
---|
30 | #define PSTOP 0x02+RO /* page stop register */ |
---|
31 | #define TPSR 0x04+RO /* tx start page start reg */ |
---|
32 | #define TBCR0 0x05+RO /* tx byte count 0 reg */ |
---|
33 | #define TBCR1 0x06+RO /* tx byte count 1 reg */ |
---|
34 | #define RSAR0 0x08+RO /* remote start address reg 0 */ |
---|
35 | #define RSAR1 0x09+RO /* remote start address reg 1 */ |
---|
36 | #define RBCR0 0x0A+RO /* remote byte count reg 0 */ |
---|
37 | #define RBCR1 0x0B+RO /* remote byte count reg 1 */ |
---|
38 | #define RCR 0x0C+RO /* rx configuration reg */ |
---|
39 | #define TCR 0x0D+RO /* tx configuration reg */ |
---|
40 | #define DCR RO+0x0E /* data configuration reg */ |
---|
41 | #define IMR 0x0F+RO /* interrupt mask reg */ |
---|
42 | |
---|
43 | /* page 1 registers */ |
---|
44 | |
---|
45 | #define PAR 0x01+RO /* physical addr reg base for rd and wr */ |
---|
46 | #define CURR 0x07+RO /* current page reg for rd and wr */ |
---|
47 | #define MAR 0x08+RO /* multicast addr reg base fro rd and WR */ |
---|
48 | #define MARsize 8 /* size of multicast addr space */ |
---|
49 | |
---|
50 | /*-----W83CREG command bits-----*/ |
---|
51 | #define MSK_RESET 0x80 /* W83CREG masks */ |
---|
52 | #define MSK_ENASH 0x40 |
---|
53 | #define MSK_DECOD 0x3F /* memory decode bits, corresponding */ |
---|
54 | /* to SA 18-13. SA 19 assumed to be 1 */ |
---|
55 | |
---|
56 | /*-----CMDR command bits-----*/ |
---|
57 | #define MSK_STP 0x01 /* stop the chip */ |
---|
58 | #define MSK_STA 0x02 /* start the chip */ |
---|
59 | #define MSK_TXP 0x04 /* initial txing of a frm */ |
---|
60 | #define MSK_RRE 0x08 /* remote read */ |
---|
61 | #define MSK_RWR 0x10 /* remote write */ |
---|
62 | #define MSK_RD2 0x20 /* no DMA used */ |
---|
63 | #define MSK_PG0 0x00 /* select register page 0 */ |
---|
64 | #define MSK_PG1 0x40 /* select register page 1 */ |
---|
65 | #define MSK_PG2 0x80 /* select register page 2 */ |
---|
66 | |
---|
67 | /*-----ISR and TSR status bits-----*/ |
---|
68 | #define MSK_PRX 0x01 /* rx with no error */ |
---|
69 | #define MSK_PTX 0x02 /* tx with no error */ |
---|
70 | #define MSK_RXE 0x04 /* rx with error */ |
---|
71 | #define MSK_TXE 0x08 /* tx with error */ |
---|
72 | #define MSK_OVW 0x10 /* overwrite warning */ |
---|
73 | #define MSK_CNT 0x20 /* MSB of one of the tally counters is set */ |
---|
74 | #define MSK_RDC 0x40 /* remote dma completed */ |
---|
75 | #define MSK_RST 0x80 /* reset state indicator */ |
---|
76 | |
---|
77 | /*-----DCR command bits-----*/ |
---|
78 | #define MSK_WTS 0x01 /* word transfer mode selection */ |
---|
79 | #define MSK_BOS 0x02 /* byte order selection */ |
---|
80 | #define MSK_LAS 0x04 /* long addr selection */ |
---|
81 | #define MSK_BMS 0x08 /* burst mode selection */ |
---|
82 | #define MSK_ARM 0x10 /* autoinitialize remote */ |
---|
83 | #define MSK_FT00 0x00 /* burst lrngth selection */ |
---|
84 | #define MSK_FT01 0x20 /* burst lrngth selection */ |
---|
85 | #define MSK_FT10 0x40 /* burst lrngth selection */ |
---|
86 | #define MSK_FT11 0x60 /* burst lrngth selection */ |
---|
87 | |
---|
88 | /*-----RCR command bits-----*/ |
---|
89 | #define MSK_SEP 0x01 /* save error pkts */ |
---|
90 | #define MSK_AR 0x02 /* accept runt pkt */ |
---|
91 | #define MSK_AB 0x04 /* 8390 RCR */ |
---|
92 | #define MSK_AM 0x08 /* accept multicast */ |
---|
93 | #define MSK_PRO 0x10 /* accept all pkt with physical adr */ |
---|
94 | #define MSK_MON 0x20 /* monitor mode */ |
---|
95 | |
---|
96 | /*-----TCR command bits-----*/ |
---|
97 | #define MSK_CRC 0x01 /* inhibit CRC, do not append crc */ |
---|
98 | #define MSK_LOOP 0x02 /* set loopback mode */ |
---|
99 | #define MSK_BCST 0x04 /* Accept broadcasts */ |
---|
100 | #define MSK_LB01 0x06 /* encoded loopback control */ |
---|
101 | #define MSK_ATD 0x08 /* auto tx disable */ |
---|
102 | #define MSK_OFST 0x10 /* collision offset enable */ |
---|
103 | |
---|
104 | /*-----receive status bits-----*/ |
---|
105 | #define SMK_PRX 0x01 /* rx without error */ |
---|
106 | #define SMK_CRC 0x02 /* CRC error */ |
---|
107 | #define SMK_FAE 0x04 /* frame alignment error */ |
---|
108 | #define SMK_FO 0x08 /* FIFO overrun */ |
---|
109 | #define SMK_MPA 0x10 /* missed pkt */ |
---|
110 | #define SMK_PHY 0x20 /* physical/multicase address */ |
---|
111 | #define SMK_DIS 0x40 /* receiver disable. set in monitor mode */ |
---|
112 | #define SMK_DEF 0x80 /* deferring */ |
---|
113 | |
---|
114 | /*-----transmit status bits-----*/ |
---|
115 | #define SMK_PTX 0x01 /* tx without error */ |
---|
116 | #define SMK_DFR 0x02 /* non deferred tx */ |
---|
117 | #define SMK_COL 0x04 /* tx collided */ |
---|
118 | #define SMK_ABT 0x08 /* tx abort because of excessive collisions */ |
---|
119 | #define SMK_CRS 0x10 /* carrier sense lost */ |
---|
120 | #define SMK_FU 0x20 /* FIFO underrun */ |
---|
121 | #define SMK_CDH 0x40 /* collision detect heartbeat */ |
---|
122 | #define SMK_OWC 0x80 /* out of window collision */ |
---|
123 | |
---|