1 | /* |
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2 | * Author: Erich Boleyn <erich@uruk.org> |
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3 | * http://www.uruk.org/~erich/ |
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4 | * |
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5 | * Copyright (c) 1997-2011 Erich Boleyn. All rights reserved. |
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6 | * |
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7 | * Redistribution and use in source and binary forms, with or without |
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8 | * modification, are permitted provided that the following conditions |
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9 | * are met: |
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10 | * 1. Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * 2. Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * 3. The name of the author may not be used to endorse or promote products |
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16 | * derived from this software without specific prior written permission. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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28 | */ |
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29 | |
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30 | /* |
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31 | * Header file implementing Intel MultiProcessor Specification (MPS) |
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32 | * version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs, |
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33 | * with hooks for running correctly on a standard PC without the hardware. |
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34 | * |
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35 | * This file was created from information in the Intel MPS version 1.4 |
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36 | * document, order number 242016-004, which can be ordered from the |
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37 | * Intel literature center. |
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38 | */ |
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39 | |
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40 | /* |
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41 | * This file is based upon code by Eric Boleyn as documented above. |
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42 | * RTEMS support was added and minimal other changes were made. |
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43 | * This should make it easier to compare this file with the original |
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44 | * version. |
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45 | * |
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46 | * COPYRIGHT (c) 2011. |
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47 | * On-Line Applications Research Corporation (OAR). |
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48 | * |
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49 | * The license and distribution terms for this file may be |
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50 | * found in the file LICENSE in this distribution or at |
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51 | * http://www.rtems.com/license/LICENSE. |
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52 | * |
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53 | * $Id$ |
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54 | */ |
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55 | |
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56 | #ifndef _SMP_IMPS_H |
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57 | #define _SMP_IMPS_H |
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58 | |
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59 | /* make sure "apic.h" is included */ |
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60 | #ifndef _APIC_H |
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61 | #error Must include "apic.h" before "smp-imps.h" |
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62 | #endif /* !_APIC_H */ |
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63 | |
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64 | /* |
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65 | * Defines used. |
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66 | */ |
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67 | |
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68 | #define IMPS_READ(x) (*((volatile unsigned *) (x))) |
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69 | #define IMPS_WRITE(x,y) (*((volatile unsigned *) (x)) = (y)) |
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70 | |
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71 | #ifdef IMPS_DEBUG |
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72 | #define IMPS_DEBUG_PRINT(x) KERNEL_PRINT(x) |
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73 | #else /* !IMPS_DEBUG */ |
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74 | #define IMPS_DEBUG_PRINT(x) |
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75 | #endif /* !IMPS_DEBUG */ |
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76 | |
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77 | #define IMPS_MAX_CPUS APIC_BCAST_ID |
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78 | |
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79 | /* |
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80 | * This is the value that must be in the "sig" member of the MP |
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81 | * Floating Pointer Structure. |
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82 | */ |
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83 | #define IMPS_FPS_SIGNATURE ('_' | ('M'<<8) | ('P'<<16) | ('_'<<24)) |
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84 | #define IMPS_FPS_IMCRP_BIT 0x80 |
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85 | #define IMPS_FPS_DEFAULT_MAX 7 |
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86 | |
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87 | /* |
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88 | * This is the value that must be in the "sig" member of the MP |
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89 | * Configuration Table Header. |
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90 | */ |
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91 | #define IMPS_CTH_SIGNATURE ('P' | ('C'<<8) | ('M'<<16) | ('P'<<24)) |
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92 | |
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93 | /* |
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94 | * These are the "type" values for Base MP Configuration Table entries. |
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95 | */ |
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96 | #define IMPS_FLAG_ENABLED 1 |
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97 | #define IMPS_BCT_PROCESSOR 0 |
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98 | #define IMPS_CPUFLAG_BOOT 2 |
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99 | #define IMPS_BCT_BUS 1 |
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100 | #define IMPS_BCT_IOAPIC 2 |
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101 | #define IMPS_BCT_IO_INTERRUPT 3 |
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102 | #define IMPS_BCT_LOCAL_INTERRUPT 4 |
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103 | #define IMPS_INT_INT 0 |
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104 | #define IMPS_INT_NMI 1 |
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105 | #define IMPS_INT_SMI 2 |
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106 | #define IMPS_INT_EXTINT 3 |
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107 | |
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108 | |
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109 | /* |
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110 | * Typedefs and data item definitions done here. |
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111 | */ |
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112 | |
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113 | typedef struct imps_fps imps_fps; /* MP floating pointer structure */ |
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114 | typedef struct imps_cth imps_cth; /* MP configuration table header */ |
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115 | typedef struct imps_processor imps_processor; |
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116 | typedef struct imps_bus imps_bus; |
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117 | typedef struct imps_ioapic imps_ioapic; |
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118 | typedef struct imps_interrupt imps_interrupt; |
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119 | |
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120 | |
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121 | /* |
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122 | * Data structures defined here |
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123 | */ |
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124 | |
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125 | /* |
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126 | * MP Floating Pointer Structure (fps) |
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127 | * |
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128 | * Look at page 4-3 of the MP spec for the starting definitions of |
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129 | * this structure. |
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130 | */ |
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131 | struct imps_fps |
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132 | { |
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133 | unsigned sig; |
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134 | imps_cth *cth_ptr; |
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135 | unsigned char length; |
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136 | unsigned char spec_rev; |
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137 | unsigned char checksum; |
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138 | unsigned char feature_info[5]; |
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139 | }; |
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140 | |
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141 | /* |
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142 | * MP Configuration Table Header (cth) |
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143 | * |
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144 | * Look at page 4-5 of the MP spec for the starting definitions of |
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145 | * this structure. |
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146 | */ |
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147 | struct imps_cth |
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148 | { |
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149 | unsigned sig; |
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150 | unsigned short base_length; |
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151 | unsigned char spec_rev; |
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152 | unsigned char checksum; |
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153 | char oem_id[8]; |
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154 | char prod_id[12]; |
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155 | unsigned oem_table_ptr; |
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156 | unsigned short oem_table_size; |
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157 | unsigned short entry_count; |
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158 | unsigned lapic_addr; |
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159 | unsigned short extended_length; |
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160 | unsigned char extended_checksum; |
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161 | char reserved[1]; |
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162 | }; |
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163 | |
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164 | /* |
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165 | * Base MP Configuration Table Types. They are sorted according to |
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166 | * type (i.e. all of type 0 come first, etc.). Look on page 4-6 for |
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167 | * the start of the descriptions. |
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168 | */ |
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169 | |
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170 | struct imps_processor |
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171 | { |
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172 | unsigned char type; /* must be 0 */ |
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173 | unsigned char apic_id; |
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174 | unsigned char apic_ver; |
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175 | unsigned char flags; |
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176 | unsigned signature; |
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177 | unsigned features; |
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178 | char reserved[8]; |
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179 | }; |
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180 | |
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181 | struct imps_bus |
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182 | { |
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183 | unsigned char type; /* must be 1 */ |
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184 | unsigned char id; |
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185 | char bus_type[6]; |
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186 | }; |
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187 | |
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188 | struct imps_ioapic |
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189 | { |
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190 | unsigned char type; /* must be 2 */ |
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191 | unsigned char id; |
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192 | unsigned char ver; |
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193 | unsigned char flags; |
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194 | unsigned addr; |
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195 | }; |
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196 | |
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197 | struct imps_interrupt |
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198 | { |
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199 | unsigned char type; /* must be 3 or 4 */ |
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200 | unsigned char int_type; |
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201 | unsigned short flags; |
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202 | unsigned char source_bus_id; |
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203 | unsigned char source_bus_irq; |
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204 | unsigned char dest_apic_id; |
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205 | unsigned char dest_apic_intin; |
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206 | }; |
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207 | |
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208 | /* |
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209 | * Exported globals here. |
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210 | */ |
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211 | |
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212 | /* |
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213 | * These map from virtual cpu numbers to APIC id's and back. |
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214 | */ |
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215 | extern unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS]; |
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216 | extern unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS]; |
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217 | |
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218 | /* base address of application processor reset code at 0x70000 */ |
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219 | extern char _binary_appstart_bin_start[]; |
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220 | extern char _binary_appstart_bin_size[]; |
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221 | |
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222 | /* |
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223 | * Defines that use variables |
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224 | */ |
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225 | #define IMPS_LAPIC_READ(x) (*((volatile unsigned *) (imps_lapic_addr+(x)))) |
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226 | #define IMPS_LAPIC_WRITE(x, y) \ |
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227 | (*((volatile unsigned *) (imps_lapic_addr+(x))) = (y)) |
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228 | |
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229 | #endif /* !_SMP_IMPS_H */ |
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230 | |
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