source: rtems/c/src/lib/libbsp/i386/shared/smp/smp-imps.c @ 8cacceb

4.115
Last change on this file since 8cacceb was 8cacceb, checked in by Sebastian Huber <sebastian.huber@…>, on May 14, 2013 at 11:23:10 AM

smp: Delete bsp_smp_secondary_cpu_initialize()

Do not call bsp_smp_secondary_cpu_initialize() in
rtems_smp_secondary_cpu_initialize(). This allows more flexibilty in
the BSP low-level code. Specify context requirements for a call to
rtems_smp_secondary_cpu_initialize().

  • Property mode set to 100644
File size: 22.9 KB
Line 
1/*
2 * Author: Erich Boleyn  <erich@uruk.org>
3 *         http://www.uruk.org/~erich/
4 *
5 * Copyright (c) 1997-2011 Erich Boleyn.  All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 *    derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 *  Source file implementing Intel MultiProcessor Specification (MPS)
32 *  version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs,
33 *  with hooks for running correctly on a standard PC without the hardware.
34 *
35 *  This file was created from information in the Intel MPS version 1.4
36 *  document, order number 242016-004, which can be ordered from the
37 *  Intel literature center.
38 *
39 *  General limitations of this code:
40 *
41 *   (1) : This code has never been tested on an MPS-compatible system with
42 *           486 CPUs, but is expected to work.
43 *   (2) : Presumes "int", "long", and "unsigned" are 32 bits in size, and
44 *       that 32-bit pointers and memory addressing is used uniformly.
45 */
46
47#define _SMP_IMPS_C
48
49/*
50 *  Includes here
51 */
52#if 0
53#define IMPS_DEBUG
54#endif
55
56#include <bsp/apic.h>
57#include <bsp/smp-imps.h>
58
59/*
60 *  XXXXX  The following absolutely must be defined!!!
61 *
62 *  The "KERNEL_PRINT" could be made a null macro with no danger, of
63 *  course, but pretty much nothing would work without the other
64 *  ones defined.
65 */
66
67#if 0
68#define KERNEL_PRINT(x)       /* some kind of print function */
69#define CMOS_WRITE_BYTE(x,y)  /* write unsigned char "y" at CMOS loc "x" */
70#define CMOS_READ_BYTE(x)     /* read unsigned char at CMOS loc "x" */
71#define PHYS_TO_VIRTUAL(x)    /* convert physical address "x" to virtual */
72#define VIRTUAL_TO_PHYS(x)    /* convert virtual address "x" to physical */
73#define UDELAY(x)             /* delay roughly at least "x" microsecs */
74#define TEST_BOOTED(x)        /* test bootaddr x to see if CPU started */
75#define READ_MSR_LO(x)        /* Read MSR low function */
76#else
77#include <string.h>
78#include <unistd.h>
79#include <rtems.h>
80#include <rtems/bspsmp.h>
81#include <rtems/bspIo.h>
82#include <libcpu/cpu.h>
83
84extern void _pc386_delay(void);
85
86/* #define KERNEL_PRINT(_format)       printk(_format) */
87
88static void CMOS_WRITE_BYTE(
89  unsigned int  offset,
90  unsigned char value
91)
92{
93  if ( offset < 128 ) {
94    outport_byte( 0x70, offset );
95    outport_byte( 0x71, value );
96  } else {
97    outport_byte( 0x72, offset );
98    outport_byte( 0x73, value );
99  }
100}
101
102static unsigned char CMOS_READ_BYTE(
103  unsigned int  offset
104)
105{
106  unsigned char value;
107  if ( offset < 128 ) {
108    outport_byte( 0x70, offset );
109    inport_byte( 0x71, value );
110  } else {
111    outport_byte( 0x72, offset );
112    inport_byte( 0x73, value );
113  }
114  return value;
115}
116
117#define PHYS_TO_VIRTUAL(_x)    _x
118#define VIRTUAL_TO_PHYS(_x)    _x
119static void UDELAY(int x)
120{ int _i = x;
121  while ( _i-- )
122    _pc386_delay();
123}
124 
125#define READ_MSR_LO(_x) \
126  (unsigned int)(read_msr(_x) & 0xffffffff)
127
128#define TEST_BOOTED(_cpu) \
129  (_Per_CPU_Information[_cpu].state == RTEMS_BSP_SMP_CPU_INITIALIZED)
130
131static inline unsigned long long read_msr(unsigned int msr)
132{
133  unsigned long long value;
134 
135  asm volatile("rdmsr" : "=A" (value) : "c" (msr));
136  return value;
137}
138#endif
139
140/*
141 *  Defines that are here so as not to be in the global header file.
142 */
143#define EBDA_SEG_ADDR       0x40E
144#define BIOS_RESET_VECTOR   0x467
145#define LAPIC_ADDR_DEFAULT  0xFEE00000uL
146#define IOAPIC_ADDR_DEFAULT 0xFEC00000uL
147#define CMOS_RESET_CODE     0xF
148#define CMOS_RESET_JUMP     0xa
149#define CMOS_BASE_MEMORY    0x15
150
151/*
152 *  Static defines here for SMP use.
153 */
154
155#define DEF_ENTRIES  23
156
157static struct {
158  imps_processor proc[2];
159  imps_bus bus[2];
160  imps_ioapic ioapic;
161  imps_interrupt intin[16];
162  imps_interrupt lintin[2];
163} defconfig = {
164  { { IMPS_BCT_PROCESSOR, 0, 0, 0, 0, 0},
165    { IMPS_BCT_PROCESSOR, 1, 0, 0, 0, 0} },
166  { { IMPS_BCT_BUS, 0, {'E', 'I', 'S', 'A', ' ', ' '}},
167    { 255, 1, {'P', 'C', 'I', ' ', ' ', ' '}} },
168  { IMPS_BCT_IOAPIC, 0, 0, IMPS_FLAG_ENABLED, IOAPIC_ADDR_DEFAULT },
169  { { IMPS_BCT_IO_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 0, 0xFF, 0},
170    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 1, 0xFF, 1},
171    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 0, 0xFF, 2},
172    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 3, 0xFF, 3},
173    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 4, 0xFF, 4},
174    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 5, 0xFF, 5},
175    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 6, 0xFF, 6},
176    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 7, 0xFF, 7},
177    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 8, 0xFF, 8},
178    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 9, 0xFF, 9},
179    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 10, 0xFF, 10},
180    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 11, 0xFF, 11},
181    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 12, 0xFF, 12},
182    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 13, 0xFF, 13},
183    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 14, 0xFF, 14},
184    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 15, 0xFF, 15} },
185  { { IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 15, 0xFF, 0},
186    { IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_NMI, 0, 0, 15, 0xFF, 1} }
187};
188
189/*
190 *  Exported globals here.
191 */
192
193volatile int imps_release_cpus = 0;
194int imps_enabled = 0;
195int imps_num_cpus = 1;
196unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS];
197unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS];
198
199/* now defined in getcpuid.c */
200extern unsigned imps_lapic_addr;
201
202static void secondary_cpu_initialize(void);
203
204/*
205 *  MPS checksum function
206 *
207 *  Function finished.
208 */
209static int
210get_checksum(unsigned start, int length)
211{
212  unsigned sum = 0;
213
214  while (length-- > 0) {
215    sum += *((unsigned char *) (start++));
216  }
217
218  return (sum&0xFF);
219}
220
221/*
222 *  APIC ICR write and status check function.
223 */
224static int
225send_ipi(unsigned int dst, unsigned int v)
226{
227  int to, send_status;
228
229  IMPS_LAPIC_WRITE(LAPIC_ICR+0x10, (dst << 24));
230  IMPS_LAPIC_WRITE(LAPIC_ICR, v);
231
232  /* Wait for send to finish */
233  to = 0;
234  do {
235    UDELAY(100);
236    send_status = IMPS_LAPIC_READ(LAPIC_ICR) & LAPIC_ICR_STATUS_PEND;
237  } while (send_status && (to++ < 1000));
238
239  return (to < 1000);
240}
241
242/*
243 *  Primary function for booting individual CPUs.
244 *
245 *  This must be modified to perform whatever OS-specific initialization
246 *  that is required.
247 */
248int
249boot_cpu(imps_processor *proc)
250{
251  int apicid = proc->apic_id, success = 1;
252  unsigned bootaddr, accept_status;
253  unsigned bios_reset_vector = PHYS_TO_VIRTUAL(BIOS_RESET_VECTOR);
254
255  /*
256   * Copy boot code for secondary CPUs here.  Find it in between
257   * "patch_code_start" and "patch_code_end" symbols.  The other CPUs
258   * will start there in 16-bit real mode under the 1MB boundary.
259   * "patch_code_start" should be placed at a 4K-aligned address
260   * under the 1MB boundary.
261   */
262
263  uint32_t *reset;
264
265  bootaddr = (512-64)*1024;
266  reset= (uint32_t *)bootaddr;
267
268  memcpy(
269    (char *) bootaddr,
270    _binary_appstart_bin_start,
271    (size_t)_binary_appstart_bin_size
272  );
273
274  reset[1] = (uint32_t)secondary_cpu_initialize;
275  reset[2] = (uint32_t)_Per_CPU_Information[apicid].interrupt_stack_high;
276
277  /*
278   *  Generic CPU startup sequence starts here.
279   */
280
281  /* set BIOS reset vector */
282  CMOS_WRITE_BYTE(CMOS_RESET_CODE, CMOS_RESET_JUMP);
283  *((volatile unsigned *) bios_reset_vector) = ((bootaddr & 0xFF000) << 12);
284
285  /* clear the APIC error register */
286  IMPS_LAPIC_WRITE(LAPIC_ESR, 0);
287  accept_status = IMPS_LAPIC_READ(LAPIC_ESR);
288
289  /* assert INIT IPI */
290  send_ipi(
291    apicid,
292    LAPIC_ICR_TM_LEVEL | LAPIC_ICR_LEVELASSERT | LAPIC_ICR_DM_INIT
293  );
294  UDELAY(10000);
295
296  /* de-assert INIT IPI */
297  send_ipi(apicid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_DM_INIT);
298
299  UDELAY(10000);
300
301  /*
302   *  Send Startup IPIs if not an old pre-integrated APIC.
303   */
304
305  if (proc->apic_ver >= APIC_VER_NEW) {
306    int i;
307    for (i = 1; i <= 2; i++) {
308      send_ipi(apicid, LAPIC_ICR_DM_SIPI | ((bootaddr >> 12) & 0xFF));
309      UDELAY(1000);
310    }
311  }
312
313  /*
314   *  Check to see if other processor has started.
315   */
316  bsp_smp_wait_for(
317    (volatile unsigned int *)&_Per_CPU_Information[imps_num_cpus].state,
318    RTEMS_BSP_SMP_CPU_INITIALIZED,
319    1600
320  );
321  if ( _Per_CPU_Information[imps_num_cpus].state ==
322        RTEMS_BSP_SMP_CPU_INITIALIZED )
323    printk("#%d  Application Processor (AP)", imps_num_cpus);
324  else {
325    printk("CPU Not Responding, DISABLED");
326    success = 0;
327  }
328
329  /*
330   *  Generic CPU startup sequence ends here, the rest is cleanup.
331   */
332
333  /* clear the APIC error register */
334  IMPS_LAPIC_WRITE(LAPIC_ESR, 0);
335  accept_status = IMPS_LAPIC_READ(LAPIC_ESR);
336
337  /* clean up BIOS reset vector */
338  CMOS_WRITE_BYTE(CMOS_RESET_CODE, 0);
339  *((volatile unsigned *) bios_reset_vector) = 0;
340
341  printk("\n");
342
343  return success;
344}
345
346/*
347 *  read bios stuff and fill tables
348 */
349static void
350add_processor(imps_processor *proc)
351{
352  int apicid = proc->apic_id;
353
354  printk("  Processor [APIC id %d ver %d]: ", apicid, proc->apic_ver);
355  if (!(proc->flags & IMPS_FLAG_ENABLED)) {
356    printk("DISABLED\n");
357    return;
358  }
359  if (proc->flags & (IMPS_CPUFLAG_BOOT)) {
360    printk("#0  BootStrap Processor (BSP)\n");
361    return;
362  }
363  if (boot_cpu(proc)) {
364
365    /*  XXXXX  add OS-specific setup for secondary CPUs here */
366
367    imps_cpu_apic_map[imps_num_cpus] = apicid;
368    imps_apic_cpu_map[apicid] = imps_num_cpus;
369    imps_num_cpus++;
370  }
371}
372
373
374static void
375add_bus(imps_bus *bus)
376{
377  char str[8];
378
379  memcpy(str, bus->bus_type, 6);
380  str[6] = 0;
381  printk("  Bus id %d is %s\n", bus->id, str);
382
383  /*  XXXXX  add OS-specific code here */
384}
385
386static void
387add_ioapic(imps_ioapic *ioapic)
388{
389  printk("  I/O APIC id %d ver %d, address: 0x%x  ",
390          ioapic->id, ioapic->ver, ioapic->addr);
391  if (!(ioapic->flags & IMPS_FLAG_ENABLED)) {
392    printk("DISABLED\n");
393    return;
394  }
395  printk("\n");
396
397  /*  XXXXX  add OS-specific code here */
398}
399
400static void
401imps_read_config_table(unsigned start, int count)
402{
403  while (count-- > 0) {
404    switch (*((unsigned char *)start)) {
405    case IMPS_BCT_PROCESSOR:
406      if ( imps_num_cpus < rtems_configuration_get_maximum_processors() ) {
407        add_processor((imps_processor *)start);
408      } else 
409        imps_num_cpus++;
410      start += 12;  /* 20 total */
411      break;
412    case IMPS_BCT_BUS:
413      add_bus((imps_bus *)start);
414      break;
415    case IMPS_BCT_IOAPIC:
416      add_ioapic((imps_ioapic *)start);
417      break;
418#if 0  /*  XXXXX  uncomment this if "add_io_interrupt" is implemented */
419    case IMPS_BCT_IO_INTERRUPT:
420      add_io_interrupt((imps_interrupt *)start);
421      break;
422#endif
423#if 0  /*  XXXXX  uncomment this if "add_local_interrupt" is implemented */
424    case IMPS_BCT_LOCAL_INTERRUPT:
425      add_local_interupt((imps_interrupt *)start);
426      break;
427#endif
428    default:
429      break;
430    }
431    start += 8;
432  }
433  if ( imps_num_cpus > rtems_configuration_get_maximum_processors() ) {
434    printk(
435      "WARNING!! Found more CPUs (%d) than configured for (%d)!!\n",
436      imps_num_cpus - 1,
437      rtems_configuration_get_maximum_processors()
438    );
439    imps_num_cpus = rtems_configuration_get_maximum_processors();
440    return;
441  }
442}
443
444static int
445imps_bad_bios(imps_fps *fps_ptr)
446{
447  int sum;
448  imps_cth *local_cth_ptr
449    = (imps_cth *) PHYS_TO_VIRTUAL(fps_ptr->cth_ptr);
450
451  if (fps_ptr->feature_info[0] > IMPS_FPS_DEFAULT_MAX) {
452    printk("    Invalid MP System Configuration type %d\n",
453            fps_ptr->feature_info[0]);
454    return 1;
455  }
456
457  if (fps_ptr->cth_ptr) {
458    sum = get_checksum((unsigned)local_cth_ptr,
459                                   local_cth_ptr->base_length);
460    if (local_cth_ptr->sig != IMPS_CTH_SIGNATURE || sum) {
461      printk(
462        "    Bad MP Config Table sig 0x%x and/or checksum 0x%x\n",
463        (unsigned)(fps_ptr->cth_ptr),
464        sum
465      );
466      return 1;
467    }
468    if (local_cth_ptr->spec_rev != fps_ptr->spec_rev) {
469      printk(
470        "    Bad MP Config Table sub-revision # %d\n",
471        local_cth_ptr->spec_rev
472      );
473      return 1;
474    }
475    if (local_cth_ptr->extended_length) {
476      sum = (get_checksum(((unsigned)local_cth_ptr)
477              + local_cth_ptr->base_length,
478              local_cth_ptr->extended_length)
479             + local_cth_ptr->extended_checksum) & 0xFF;
480      if (sum) {
481        printk("    Bad Extended MP Config Table checksum 0x%x\n", sum);
482        return 1;
483      }
484    }
485  } else if (!fps_ptr->feature_info[0]) {
486    printk("    Missing configuration information\n");
487    return 1;
488  }
489
490  return 0;
491}
492
493static void
494imps_read_bios(imps_fps *fps_ptr)
495{
496  int apicid;
497  unsigned cth_start, cth_count;
498  imps_cth *local_cth_ptr
499    = (imps_cth *)PHYS_TO_VIRTUAL(fps_ptr->cth_ptr);
500  char *str_ptr;
501
502  printk("Intel MultiProcessor Spec 1.%d BIOS support detected\n",
503          fps_ptr->spec_rev);
504
505  /*
506   *  Do all checking of errors which would definitely
507   *  lead to failure of the SMP boot here.
508   */
509  if (imps_bad_bios(fps_ptr)) {
510    printk("    Disabling MPS support\n");
511    return;
512  }
513
514  if (fps_ptr->feature_info[1] & IMPS_FPS_IMCRP_BIT) {
515    str_ptr = "IMCR and PIC";
516  } else {
517    str_ptr = "Virtual Wire";
518  }
519  if (fps_ptr->cth_ptr) {
520    imps_lapic_addr = local_cth_ptr->lapic_addr;
521  } else {
522    imps_lapic_addr = LAPIC_ADDR_DEFAULT;
523  }
524  printk("    APIC config: \"%s mode\"    Local APIC address: 0x%x\n",
525          str_ptr, imps_lapic_addr);
526  if (imps_lapic_addr != (READ_MSR_LO(0x1b) & 0xFFFFF000)) {
527    printk("Inconsistent Local APIC address, Disabling SMP support\n");
528    return;
529  }
530  imps_lapic_addr = PHYS_TO_VIRTUAL(imps_lapic_addr);
531
532  /*
533   *  Setup primary CPU.
534   */
535  apicid = IMPS_LAPIC_READ(LAPIC_SPIV);
536  IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC);
537  apicid = APIC_ID(IMPS_LAPIC_READ(LAPIC_ID));
538  imps_cpu_apic_map[0] = apicid;
539  imps_apic_cpu_map[apicid] = 0;
540
541  if (fps_ptr->cth_ptr) {
542    char str1[16], str2[16];
543    memcpy(str1, local_cth_ptr->oem_id, 8);
544    str1[8] = 0;
545    memcpy(str2, local_cth_ptr->prod_id, 12);
546    str2[12] = 0;
547    printk("  OEM id: %s  Product id: %s\n", str1, str2);
548    cth_start = ((unsigned) local_cth_ptr) + sizeof(imps_cth);
549    cth_count = local_cth_ptr->entry_count;
550  } else {
551    *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) =  IOAPIC_ID;
552    defconfig.ioapic.id
553      = APIC_ID(*((volatile unsigned *)
554            (IOAPIC_ADDR_DEFAULT+IOAPIC_RW)));
555    *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) =  IOAPIC_VER;
556    defconfig.ioapic.ver
557      = APIC_VERSION(*((volatile unsigned *)
558           (IOAPIC_ADDR_DEFAULT+IOAPIC_RW)));
559    defconfig.proc[apicid].flags
560      = IMPS_FLAG_ENABLED|IMPS_CPUFLAG_BOOT;
561    defconfig.proc[!apicid].flags = IMPS_FLAG_ENABLED;
562    imps_num_cpus = 2;
563    if (fps_ptr->feature_info[0] == 1
564     || fps_ptr->feature_info[0] == 5) {
565      memcpy(defconfig.bus[0].bus_type, "ISA   ", 6);
566    }
567    if (fps_ptr->feature_info[0] == 4
568     || fps_ptr->feature_info[0] == 7) {
569      memcpy(defconfig.bus[0].bus_type, "MCA   ", 6);
570    }
571    if (fps_ptr->feature_info[0] > 4) {
572      defconfig.proc[0].apic_ver = 0x10;
573      defconfig.proc[1].apic_ver = 0x10;
574      defconfig.bus[1].type = IMPS_BCT_BUS;
575    }
576    if (fps_ptr->feature_info[0] == 2) {
577      defconfig.intin[2].type = 255;
578      defconfig.intin[13].type = 255;
579    }
580    if (fps_ptr->feature_info[0] == 7) {
581      defconfig.intin[0].type = 255;
582    }
583    cth_start = (unsigned) &defconfig;
584    cth_count = DEF_ENTRIES;
585  }
586  imps_read_config_table(cth_start, cth_count);
587
588  /* %%%%% ESB read extended entries here */
589
590  imps_enabled = 1;
591}
592
593/*
594 *  Given a region to check, this actually looks for the "MP Floating
595 *  Pointer Structure".  The return value indicates if the correct
596 *  signature and checksum for a floating pointer structure of the
597 *  appropriate spec revision was found.  If so, then do not search
598 *  further.
599 *
600 *  NOTE:  The memory scan will always be in the bottom 1 MB.
601 *
602 *  This function presumes that "start" will always be aligned to a 16-bit
603 *  boundary.
604 *
605 *  Function finished.
606 */
607static int
608imps_scan(unsigned start, unsigned length)
609{
610  printk("Scanning from 0x%x for %d bytes\n", start, length);
611
612  while (length > 0) {
613    imps_fps *fps_ptr = (imps_fps *) PHYS_TO_VIRTUAL(start);
614
615    if (fps_ptr->sig == IMPS_FPS_SIGNATURE
616     && fps_ptr->length == 1
617     && (fps_ptr->spec_rev == 1 || fps_ptr->spec_rev == 4)
618     && !get_checksum(start, 16)) {
619      printk("Found MP Floating Structure Pointer at %x\n", start);
620      imps_read_bios(fps_ptr);
621      return 1;
622    }
623
624    length -= 16;
625    start += 16;
626  }
627
628  return 0;
629}
630
631#if !defined(__rtems__)
632/*
633 *  This is the primary function to "force" SMP support, with
634 *  the assumption that you have consecutively numbered APIC ids.
635 */
636int
637imps_force(int ncpus)
638{
639  int apicid, i;
640  imps_processor p;
641
642  printk("Intel MultiProcessor \"Force\" Support\n");
643
644  imps_lapic_addr = (READ_MSR_LO(0x1b) & 0xFFFFF000);
645  imps_lapic_addr = PHYS_TO_VIRTUAL(imps_lapic_addr);
646
647  /*
648   *  Setup primary CPU.
649   */
650  apicid = IMPS_LAPIC_READ(LAPIC_SPIV);
651  IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC);
652  apicid = APIC_ID(IMPS_LAPIC_READ(LAPIC_ID));
653  imps_cpu_apic_map[0] = apicid;
654  imps_apic_cpu_map[apicid] = 0;
655
656  p.type = 0;
657  p.apic_ver = 0x10;
658  p.signature = p.features = 0;
659
660  for (i = 0; i < ncpus; i++) {
661    if (apicid == i) {
662      p.flags = IMPS_FLAG_ENABLED | IMPS_CPUFLAG_BOOT;
663    } else {
664      p.flags = IMPS_FLAG_ENABLED;
665    }
666    p.apic_id = i;
667    add_processor(&p);
668  }
669
670  return imps_num_cpus;
671}
672#endif
673
674/*
675 *  This is the primary function for probing for MPS compatible hardware
676 *  and BIOS information.  Call this during the early stages of OS startup,
677 *  before memory can be messed up.
678 *
679 *  The probe looks for the "MP Floating Pointer Structure" at locations
680 *  listed at the top of page 4-2 of the spec.
681 *
682 *  Environment requirements from the OS to run:
683 *
684 *   (1) : A non-linear virtual to physical memory mapping is probably OK,
685 *       as (I think) the structures all fall within page boundaries,
686 *       but a linear mapping is recommended.  Currently assumes that
687 *       the mapping will remain identical over time (which should be
688 *       OK since it only accesses memory which shouldn't be munged
689 *       by the OS anyway).
690 *   (2) : The OS only consumes memory which the BIOS says is OK to use,
691 *       and not any of the BIOS standard areas (the areas 0x400 to
692 *       0x600, the EBDA, 0xE0000 to 0xFFFFF, and unreported physical
693 *       RAM).  Sometimes a small amount of physical RAM is not
694 *       reported by the BIOS, to be used to store MPS and other
695 *       information.
696 *   (3) : It must be possible to read the CMOS.
697 *   (4) : There must be between 512K and 640K of lower memory (this is a
698 *       sanity check).
699 *
700 *  Function finished.
701 */
702int
703imps_probe(void)
704{
705  /*
706   *  Determine possible address of the EBDA
707   */
708  unsigned ebda_addr = *((unsigned short *)
709             PHYS_TO_VIRTUAL(EBDA_SEG_ADDR)) << 4;
710
711  /*
712   *  Determine amount of installed lower memory (not *available*
713   *  lower memory).
714   *
715   *  NOTE:  This should work reliably as long as we verify the
716   *         machine is at least a system that could possibly have
717   *         MPS compatibility to begin with.
718   */
719  unsigned mem_lower = ((CMOS_READ_BYTE(CMOS_BASE_MEMORY+1) << 8)
720            | CMOS_READ_BYTE(CMOS_BASE_MEMORY))       << 10;
721
722#ifdef IMPS_DEBUG
723  imps_enabled = 0;
724  imps_num_cpus = 1;
725#endif
726
727  /*
728   *  Sanity check : if this isn't reasonable, it is almost impossibly
729   *    unlikely to be an MPS compatible machine, so return failure.
730   */
731  if (mem_lower < 512*1024 || mem_lower > 640*1024) {
732    return 0;
733  }
734
735  if (ebda_addr > mem_lower - 1024
736   || ebda_addr + *((unsigned char *) PHYS_TO_VIRTUAL(ebda_addr))
737         * 1024 > mem_lower) {
738    ebda_addr = 0;
739  }
740
741  if (((ebda_addr && imps_scan(ebda_addr, 1024))
742   || (!ebda_addr && imps_scan(mem_lower - 1024, 1024))
743   || imps_scan(0xF0000, 0x10000)) && imps_enabled) {
744    return imps_num_cpus;
745  }
746
747  /*
748   *  If no BIOS info on MPS hardware is found, then return failure.
749   */
750
751  return 0;
752}
753
754/*
755 *  RTEMS SMP BSP Support
756 */
757void smp_apic_ack(void)
758{
759  (void) IMPS_LAPIC_READ(LAPIC_SPIV);  /* dummy read */
760  IMPS_LAPIC_WRITE(LAPIC_EOI, 0 );     /* ACK the interrupt */
761}
762
763rtems_isr ap_ipi_isr(
764  rtems_vector_number vector
765)
766{
767  smp_apic_ack();
768
769  rtems_smp_process_interrupt();
770}
771
772#include <rtems/irq.h>
773
774static rtems_irq_connect_data apIPIIrqData = {
775  16,
776  (void *)ap_ipi_isr,
777  0,
778  NULL,            /* On */
779  NULL,            /* Off */
780  NULL,            /* IsOn */
781};
782
783extern void bsp_reset(void);
784void ipi_install_irq(void)
785{
786  if (!BSP_install_rtems_irq_handler (&apIPIIrqData)) {
787    printk("Unable to initialize IPI\n");
788    bsp_reset();
789  }
790}
791
792#ifdef __SSE__
793extern void enable_sse(void);
794#endif
795
796/* pc386 specific initialization */
797static void secondary_cpu_initialize(void)
798{
799  int apicid;
800
801  asm volatile( "lidt IDT_Descriptor" );
802
803  apicid = IMPS_LAPIC_READ(LAPIC_SPIV);
804  IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC);
805
806#ifdef __SSE__
807  enable_sse();
808#endif
809
810  rtems_smp_secondary_cpu_initialize();
811}
812
813#include <rtems/bspsmp.h>
814uint32_t bsp_smp_initialize( uint32_t configured_cpu_count )
815{
816  int cores;
817  /* XXX need to deal with finding too many cores */
818
819  cores = imps_probe();
820
821  if ( cores > 1 )
822    ipi_install_irq();
823  return cores;
824}
825
826void bsp_smp_interrupt_cpu(
827  int cpu
828)
829{
830  send_ipi( cpu, 0x30 );
831}
832
833void bsp_smp_broadcast_interrupt(void)
834{
835  /* Single broadcast interrupt */
836  send_ipi( 0, LAPIC_ICR_DS_ALLEX | 0x30 );
837}
838
839void bsp_smp_wait_for(
840  volatile unsigned int *address,
841  unsigned int           desired,
842  int                    maximum_usecs
843)
844{
845  int iterations;
846  volatile int i;
847  volatile unsigned int *p = (volatile unsigned int *)address;
848
849  for (iterations=0 ;  iterations < maximum_usecs ; iterations++ ) {
850    if ( *p == desired )
851      break;
852    #ifdef __SSE3__
853      __builtin_ia32_monitor( (const void *)address, 0, 0 );
854      if ( *p == desired )
855        break;
856      __builtin_ia32_mwait( 0, 0 );
857    #endif
858
859    /*
860     *  Until i386 ms delay does not depend upon the clock we
861     *  will use this less sophisticated delay.
862     */
863    for(i=5000; i>0; i--)
864      ;
865  }
866}
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