source: rtems/c/src/lib/libbsp/i386/shared/smp/smp-imps.c @ 328bd35

5
Last change on this file since 328bd35 was 328bd35, checked in by Joel Sherrill <joel@…>, on Jan 23, 2016 at 7:06:22 PM

i386: refactor libcpu/cpu.h into rtems/score/i386.h

Fixes #2515.

  • Property mode set to 100644
File size: 21.7 KB
Line 
1/*
2 * Author: Erich Boleyn  <erich@uruk.org>
3 *         http://www.uruk.org/~erich/
4 *
5 * Copyright (c) 1997-2011 Erich Boleyn.  All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 *    derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 *  Source file implementing Intel MultiProcessor Specification (MPS)
32 *  version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs,
33 *  with hooks for running correctly on a standard PC without the hardware.
34 *
35 *  This file was created from information in the Intel MPS version 1.4
36 *  document, order number 242016-004, which can be ordered from the
37 *  Intel literature center.
38 *
39 *  General limitations of this code:
40 *
41 *   (1) : This code has never been tested on an MPS-compatible system with
42 *           486 CPUs, but is expected to work.
43 *   (2) : Presumes "int", "long", and "unsigned" are 32 bits in size, and
44 *       that 32-bit pointers and memory addressing is used uniformly.
45 */
46
47#define _SMP_IMPS_C
48
49/*
50 *  Includes here
51 */
52#if 0
53#define IMPS_DEBUG
54#endif
55
56#include <bsp/apic.h>
57#include <bsp/smp-imps.h>
58#include <bsp/irq.h>
59#include <rtems/score/smpimpl.h>
60
61/*
62 *  XXXXX  The following absolutely must be defined!!!
63 *
64 *  The "KERNEL_PRINT" could be made a null macro with no danger, of
65 *  course, but pretty much nothing would work without the other
66 *  ones defined.
67 */
68
69#if 0
70#define KERNEL_PRINT(x)       /* some kind of print function */
71#define CMOS_WRITE_BYTE(x,y)  /* write unsigned char "y" at CMOS loc "x" */
72#define CMOS_READ_BYTE(x)     /* read unsigned char at CMOS loc "x" */
73#define PHYS_TO_VIRTUAL(x)    /* convert physical address "x" to virtual */
74#define VIRTUAL_TO_PHYS(x)    /* convert virtual address "x" to physical */
75#define UDELAY(x)             /* delay roughly at least "x" microsecs */
76#define READ_MSR_LO(x)        /* Read MSR low function */
77#else
78#include <string.h>
79#include <unistd.h>
80#include <rtems.h>
81#include <rtems/bspIo.h>
82#include <rtems/score/cpu.h>
83#include <assert.h>
84
85extern void _pc386_delay(void);
86
87/* #define KERNEL_PRINT(_format)       printk(_format) */
88
89static void CMOS_WRITE_BYTE(
90  unsigned int  offset,
91  unsigned char value
92)
93{
94  if ( offset < 128 ) {
95    outport_byte( 0x70, offset );
96    outport_byte( 0x71, value );
97  } else {
98    outport_byte( 0x72, offset );
99    outport_byte( 0x73, value );
100  }
101}
102
103static unsigned char CMOS_READ_BYTE(
104  unsigned int  offset
105)
106{
107  unsigned char value;
108  if ( offset < 128 ) {
109    outport_byte( 0x70, offset );
110    inport_byte( 0x71, value );
111  } else {
112    outport_byte( 0x72, offset );
113    inport_byte( 0x73, value );
114  }
115  return value;
116}
117
118#define PHYS_TO_VIRTUAL(_x)    _x
119#define VIRTUAL_TO_PHYS(_x)    _x
120static void UDELAY(int x)
121{ int _i = x;
122  while ( _i-- )
123    _pc386_delay();
124}
125
126#define READ_MSR_LO(_x) \
127  (unsigned int)(read_msr(_x) & 0xffffffff)
128
129static inline unsigned long long read_msr(unsigned int msr)
130{
131  unsigned long long value;
132
133  asm volatile("rdmsr" : "=A" (value) : "c" (msr));
134  return value;
135}
136#endif
137
138/*
139 *  Defines that are here so as not to be in the global header file.
140 */
141#define EBDA_SEG_ADDR       0x40E
142#define BIOS_RESET_VECTOR   0x467
143#define LAPIC_ADDR_DEFAULT  0xFEE00000uL
144#define IOAPIC_ADDR_DEFAULT 0xFEC00000uL
145#define CMOS_RESET_CODE     0xF
146#define CMOS_RESET_JUMP     0xa
147#define CMOS_BASE_MEMORY    0x15
148
149/*
150 *  Static defines here for SMP use.
151 */
152
153#define DEF_ENTRIES  23
154
155static struct {
156  imps_processor proc[2];
157  imps_bus bus[2];
158  imps_ioapic ioapic;
159  imps_interrupt intin[16];
160  imps_interrupt lintin[2];
161} defconfig = {
162  { { IMPS_BCT_PROCESSOR, 0, 0, 0, 0, 0},
163    { IMPS_BCT_PROCESSOR, 1, 0, 0, 0, 0} },
164  { { IMPS_BCT_BUS, 0, {'E', 'I', 'S', 'A', ' ', ' '}},
165    { 255, 1, {'P', 'C', 'I', ' ', ' ', ' '}} },
166  { IMPS_BCT_IOAPIC, 0, 0, IMPS_FLAG_ENABLED, IOAPIC_ADDR_DEFAULT },
167  { { IMPS_BCT_IO_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 0, 0xFF, 0},
168    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 1, 0xFF, 1},
169    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 0, 0xFF, 2},
170    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 3, 0xFF, 3},
171    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 4, 0xFF, 4},
172    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 5, 0xFF, 5},
173    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 6, 0xFF, 6},
174    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 7, 0xFF, 7},
175    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 8, 0xFF, 8},
176    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 9, 0xFF, 9},
177    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 10, 0xFF, 10},
178    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 11, 0xFF, 11},
179    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 12, 0xFF, 12},
180    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 13, 0xFF, 13},
181    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 14, 0xFF, 14},
182    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 15, 0xFF, 15} },
183  { { IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 15, 0xFF, 0},
184    { IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_NMI, 0, 0, 15, 0xFF, 1} }
185};
186
187/*
188 *  Exported globals here.
189 */
190
191volatile int imps_release_cpus = 0;
192int imps_enabled = 0;
193int imps_num_cpus = 1;
194unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS];
195unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS];
196
197/* now defined in getcpuid.c */
198extern unsigned imps_lapic_addr;
199
200static void secondary_cpu_initialize(void);
201
202/*
203 *  MPS checksum function
204 *
205 *  Function finished.
206 */
207static int
208get_checksum(unsigned start, int length)
209{
210  unsigned sum = 0;
211
212  while (length-- > 0) {
213    sum += *((unsigned char *) (start++));
214  }
215
216  return (sum&0xFF);
217}
218
219/*
220 *  APIC ICR write and status check function.
221 */
222static int
223send_ipi(unsigned int dst, unsigned int v)
224{
225  int to, send_status;
226
227  IMPS_LAPIC_WRITE(LAPIC_ICR+0x10, (dst << 24));
228  IMPS_LAPIC_WRITE(LAPIC_ICR, v);
229
230  /* Wait for send to finish */
231  to = 0;
232  do {
233    UDELAY(100);
234    send_status = IMPS_LAPIC_READ(LAPIC_ICR) & LAPIC_ICR_STATUS_PEND;
235  } while (send_status && (to++ < 1000));
236
237  return (to < 1000);
238}
239
240/*
241 *  Primary function for booting individual CPUs.
242 *
243 *  This must be modified to perform whatever OS-specific initialization
244 *  that is required.
245 */
246static int
247boot_cpu(imps_processor *proc)
248{
249  int apicid = proc->apic_id, success = 1;
250  unsigned bootaddr;
251  unsigned bios_reset_vector = PHYS_TO_VIRTUAL(BIOS_RESET_VECTOR);
252
253  /*
254   * Copy boot code for secondary CPUs here.  Find it in between
255   * "patch_code_start" and "patch_code_end" symbols.  The other CPUs
256   * will start there in 16-bit real mode under the 1MB boundary.
257   * "patch_code_start" should be placed at a 4K-aligned address
258   * under the 1MB boundary.
259   */
260
261  uint32_t *reset;
262
263  bootaddr = (512-64)*1024;
264  reset= (uint32_t *)bootaddr;
265
266  memcpy(
267    (char *) bootaddr,
268    _binary_appstart_bin_start,
269    (size_t)_binary_appstart_bin_size
270  );
271
272  reset[1] = (uint32_t)secondary_cpu_initialize;
273  reset[2] = (uint32_t)_Per_CPU_Get_by_index(apicid)->interrupt_stack_high;
274
275  /*
276   *  Generic CPU startup sequence starts here.
277   */
278
279  /* set BIOS reset vector */
280  CMOS_WRITE_BYTE(CMOS_RESET_CODE, CMOS_RESET_JUMP);
281  *((volatile unsigned *) bios_reset_vector) = ((bootaddr & 0xFF000) << 12);
282
283  /* clear the APIC error register */
284  IMPS_LAPIC_WRITE(LAPIC_ESR, 0);
285  IMPS_LAPIC_READ(LAPIC_ESR);
286
287  /* assert INIT IPI */
288  send_ipi(
289    apicid,
290    LAPIC_ICR_TM_LEVEL | LAPIC_ICR_LEVELASSERT | LAPIC_ICR_DM_INIT
291  );
292  UDELAY(10000);
293
294  /* de-assert INIT IPI */
295  send_ipi(apicid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_DM_INIT);
296
297  UDELAY(10000);
298
299  /*
300   *  Send Startup IPIs if not an old pre-integrated APIC.
301   */
302
303  if (proc->apic_ver >= APIC_VER_NEW) {
304    int i;
305    for (i = 1; i <= 2; i++) {
306      send_ipi(apicid, LAPIC_ICR_DM_SIPI | ((bootaddr >> 12) & 0xFF));
307      UDELAY(1000);
308    }
309  }
310
311  /*
312   *  Generic CPU startup sequence ends here, the rest is cleanup.
313   */
314
315  /* clear the APIC error register */
316  IMPS_LAPIC_WRITE(LAPIC_ESR, 0);
317  IMPS_LAPIC_READ(LAPIC_ESR);
318
319  /* clean up BIOS reset vector */
320  CMOS_WRITE_BYTE(CMOS_RESET_CODE, 0);
321  *((volatile unsigned *) bios_reset_vector) = 0;
322
323  printk("\n");
324
325  return success;
326}
327
328/*
329 *  read bios stuff and fill tables
330 */
331static void
332add_processor(imps_processor *proc)
333{
334  int apicid = proc->apic_id;
335
336  printk("  Processor [APIC id %d ver %d]: ", apicid, proc->apic_ver);
337  if (!(proc->flags & IMPS_FLAG_ENABLED)) {
338    printk("DISABLED\n");
339    return;
340  }
341  if (proc->flags & (IMPS_CPUFLAG_BOOT)) {
342    printk("#0  BootStrap Processor (BSP)\n");
343    return;
344  }
345  if (boot_cpu(proc)) {
346
347    /*  XXXXX  add OS-specific setup for secondary CPUs here */
348
349    imps_cpu_apic_map[imps_num_cpus] = apicid;
350    imps_apic_cpu_map[apicid] = imps_num_cpus;
351    imps_num_cpus++;
352  }
353}
354
355
356static void
357add_bus(imps_bus *bus)
358{
359  char str[8];
360
361  memcpy(str, bus->bus_type, 6);
362  str[6] = 0;
363  printk("  Bus id %d is %s\n", bus->id, str);
364
365  /*  XXXXX  add OS-specific code here */
366}
367
368static void
369add_ioapic(imps_ioapic *ioapic)
370{
371  printk("  I/O APIC id %d ver %d, address: 0x%x  ",
372          ioapic->id, ioapic->ver, ioapic->addr);
373  if (!(ioapic->flags & IMPS_FLAG_ENABLED)) {
374    printk("DISABLED\n");
375    return;
376  }
377  printk("\n");
378
379  /*  XXXXX  add OS-specific code here */
380}
381
382static void
383imps_read_config_table(unsigned start, int count)
384{
385  while (count-- > 0) {
386    switch (*((unsigned char *)start)) {
387    case IMPS_BCT_PROCESSOR:
388      if ( imps_num_cpus < rtems_configuration_get_maximum_processors() ) {
389        if (_SMP_Should_start_processor((uint32_t) imps_num_cpus)) {
390          add_processor((imps_processor *)start);
391        }
392      } else
393        imps_num_cpus++;
394      start += 12;  /* 20 total */
395      break;
396    case IMPS_BCT_BUS:
397      add_bus((imps_bus *)start);
398      break;
399    case IMPS_BCT_IOAPIC:
400      add_ioapic((imps_ioapic *)start);
401      break;
402#if 0  /*  XXXXX  uncomment this if "add_io_interrupt" is implemented */
403    case IMPS_BCT_IO_INTERRUPT:
404      add_io_interrupt((imps_interrupt *)start);
405      break;
406#endif
407#if 0  /*  XXXXX  uncomment this if "add_local_interrupt" is implemented */
408    case IMPS_BCT_LOCAL_INTERRUPT:
409      add_local_interupt((imps_interrupt *)start);
410      break;
411#endif
412    default:
413      break;
414    }
415    start += 8;
416  }
417  if ( imps_num_cpus > rtems_configuration_get_maximum_processors() ) {
418    printk(
419      "WARNING!! Found more CPUs (%d) than configured for (%d)!!\n",
420      imps_num_cpus - 1,
421      rtems_configuration_get_maximum_processors()
422    );
423    imps_num_cpus = rtems_configuration_get_maximum_processors();
424    return;
425  }
426}
427
428static int
429imps_bad_bios(imps_fps *fps_ptr)
430{
431  int sum;
432  imps_cth *local_cth_ptr
433    = (imps_cth *) PHYS_TO_VIRTUAL(fps_ptr->cth_ptr);
434
435  if (fps_ptr->feature_info[0] > IMPS_FPS_DEFAULT_MAX) {
436    printk("    Invalid MP System Configuration type %d\n",
437            fps_ptr->feature_info[0]);
438    return 1;
439  }
440
441  if (fps_ptr->cth_ptr) {
442    sum = get_checksum((unsigned)local_cth_ptr,
443                                   local_cth_ptr->base_length);
444    if (local_cth_ptr->sig != IMPS_CTH_SIGNATURE || sum) {
445      printk(
446        "    Bad MP Config Table sig 0x%x and/or checksum 0x%x\n",
447        (unsigned)(fps_ptr->cth_ptr),
448        sum
449      );
450      return 1;
451    }
452    if (local_cth_ptr->spec_rev != fps_ptr->spec_rev) {
453      printk(
454        "    Bad MP Config Table sub-revision # %d\n",
455        local_cth_ptr->spec_rev
456      );
457      return 1;
458    }
459    if (local_cth_ptr->extended_length) {
460      sum = (get_checksum(((unsigned)local_cth_ptr)
461              + local_cth_ptr->base_length,
462              local_cth_ptr->extended_length)
463             + local_cth_ptr->extended_checksum) & 0xFF;
464      if (sum) {
465        printk("    Bad Extended MP Config Table checksum 0x%x\n", sum);
466        return 1;
467      }
468    }
469  } else if (!fps_ptr->feature_info[0]) {
470    printk("    Missing configuration information\n");
471    return 1;
472  }
473
474  return 0;
475}
476
477static void
478imps_read_bios(imps_fps *fps_ptr)
479{
480  int apicid;
481  unsigned cth_start, cth_count;
482  imps_cth *local_cth_ptr
483    = (imps_cth *)PHYS_TO_VIRTUAL(fps_ptr->cth_ptr);
484  char *str_ptr;
485
486  printk("Intel MultiProcessor Spec 1.%d BIOS support detected\n",
487          fps_ptr->spec_rev);
488
489  /*
490   *  Do all checking of errors which would definitely
491   *  lead to failure of the SMP boot here.
492   */
493  if (imps_bad_bios(fps_ptr)) {
494    printk("    Disabling MPS support\n");
495    return;
496  }
497
498  if (fps_ptr->feature_info[1] & IMPS_FPS_IMCRP_BIT) {
499    str_ptr = "IMCR and PIC";
500  } else {
501    str_ptr = "Virtual Wire";
502  }
503  if (fps_ptr->cth_ptr) {
504    imps_lapic_addr = local_cth_ptr->lapic_addr;
505  } else {
506    imps_lapic_addr = LAPIC_ADDR_DEFAULT;
507  }
508  printk("    APIC config: \"%s mode\"    Local APIC address: 0x%x\n",
509          str_ptr, imps_lapic_addr);
510  if (imps_lapic_addr != (READ_MSR_LO(0x1b) & 0xFFFFF000)) {
511    printk("Inconsistent Local APIC address, Disabling SMP support\n");
512    return;
513  }
514  imps_lapic_addr = PHYS_TO_VIRTUAL(imps_lapic_addr);
515
516  /*
517   *  Setup primary CPU.
518   */
519  apicid = IMPS_LAPIC_READ(LAPIC_SPIV);
520  IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC);
521  apicid = APIC_ID(IMPS_LAPIC_READ(LAPIC_ID));
522  imps_cpu_apic_map[0] = apicid;
523  imps_apic_cpu_map[apicid] = 0;
524
525  if (fps_ptr->cth_ptr) {
526    char str1[16], str2[16];
527    memcpy(str1, local_cth_ptr->oem_id, 8);
528    str1[8] = 0;
529    memcpy(str2, local_cth_ptr->prod_id, 12);
530    str2[12] = 0;
531    printk("  OEM id: %s  Product id: %s\n", str1, str2);
532    cth_start = ((unsigned) local_cth_ptr) + sizeof(imps_cth);
533    cth_count = local_cth_ptr->entry_count;
534  } else {
535    *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) =  IOAPIC_ID;
536    defconfig.ioapic.id
537      = APIC_ID(*((volatile unsigned *)
538            (IOAPIC_ADDR_DEFAULT+IOAPIC_RW)));
539    *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) =  IOAPIC_VER;
540    defconfig.ioapic.ver
541      = APIC_VERSION(*((volatile unsigned *)
542           (IOAPIC_ADDR_DEFAULT+IOAPIC_RW)));
543    defconfig.proc[apicid].flags
544      = IMPS_FLAG_ENABLED|IMPS_CPUFLAG_BOOT;
545    defconfig.proc[!apicid].flags = IMPS_FLAG_ENABLED;
546    imps_num_cpus = 2;
547    if (fps_ptr->feature_info[0] == 1
548     || fps_ptr->feature_info[0] == 5) {
549      memcpy(defconfig.bus[0].bus_type, "ISA   ", 6);
550    }
551    if (fps_ptr->feature_info[0] == 4
552     || fps_ptr->feature_info[0] == 7) {
553      memcpy(defconfig.bus[0].bus_type, "MCA   ", 6);
554    }
555    if (fps_ptr->feature_info[0] > 4) {
556      defconfig.proc[0].apic_ver = 0x10;
557      defconfig.proc[1].apic_ver = 0x10;
558      defconfig.bus[1].type = IMPS_BCT_BUS;
559    }
560    if (fps_ptr->feature_info[0] == 2) {
561      defconfig.intin[2].type = 255;
562      defconfig.intin[13].type = 255;
563    }
564    if (fps_ptr->feature_info[0] == 7) {
565      defconfig.intin[0].type = 255;
566    }
567    cth_start = (unsigned) &defconfig;
568    cth_count = DEF_ENTRIES;
569  }
570  imps_read_config_table(cth_start, cth_count);
571
572  /* %%%%% ESB read extended entries here */
573
574  imps_enabled = 1;
575}
576
577/*
578 *  Given a region to check, this actually looks for the "MP Floating
579 *  Pointer Structure".  The return value indicates if the correct
580 *  signature and checksum for a floating pointer structure of the
581 *  appropriate spec revision was found.  If so, then do not search
582 *  further.
583 *
584 *  NOTE:  The memory scan will always be in the bottom 1 MB.
585 *
586 *  This function presumes that "start" will always be aligned to a 16-bit
587 *  boundary.
588 *
589 *  Function finished.
590 */
591static int
592imps_scan(unsigned start, unsigned length)
593{
594  printk("Scanning from 0x%x for %d bytes\n", start, length);
595
596  while (length > 0) {
597    imps_fps *fps_ptr = (imps_fps *) PHYS_TO_VIRTUAL(start);
598
599    if (fps_ptr->sig == IMPS_FPS_SIGNATURE
600     && fps_ptr->length == 1
601     && (fps_ptr->spec_rev == 1 || fps_ptr->spec_rev == 4)
602     && !get_checksum(start, 16)) {
603      printk("Found MP Floating Structure Pointer at %x\n", start);
604      imps_read_bios(fps_ptr);
605      return 1;
606    }
607
608    length -= 16;
609    start += 16;
610  }
611
612  return 0;
613}
614
615#if !defined(__rtems__)
616/*
617 *  This is the primary function to "force" SMP support, with
618 *  the assumption that you have consecutively numbered APIC ids.
619 */
620int
621imps_force(int ncpus)
622{
623  int apicid, i;
624  imps_processor p;
625
626  printk("Intel MultiProcessor \"Force\" Support\n");
627
628  imps_lapic_addr = (READ_MSR_LO(0x1b) & 0xFFFFF000);
629  imps_lapic_addr = PHYS_TO_VIRTUAL(imps_lapic_addr);
630
631  /*
632   *  Setup primary CPU.
633   */
634  apicid = IMPS_LAPIC_READ(LAPIC_SPIV);
635  IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC);
636  apicid = APIC_ID(IMPS_LAPIC_READ(LAPIC_ID));
637  imps_cpu_apic_map[0] = apicid;
638  imps_apic_cpu_map[apicid] = 0;
639
640  p.type = 0;
641  p.apic_ver = 0x10;
642  p.signature = p.features = 0;
643
644  for (i = 0; i < ncpus; i++) {
645    if (apicid == i) {
646      p.flags = IMPS_FLAG_ENABLED | IMPS_CPUFLAG_BOOT;
647    } else {
648      p.flags = IMPS_FLAG_ENABLED;
649    }
650    p.apic_id = i;
651    add_processor(&p);
652  }
653
654  return imps_num_cpus;
655}
656#endif
657
658/*
659 *  This is the primary function for probing for MPS compatible hardware
660 *  and BIOS information.  Call this during the early stages of OS startup,
661 *  before memory can be messed up.
662 *
663 *  The probe looks for the "MP Floating Pointer Structure" at locations
664 *  listed at the top of page 4-2 of the spec.
665 *
666 *  Environment requirements from the OS to run:
667 *
668 *   (1) : A non-linear virtual to physical memory mapping is probably OK,
669 *       as (I think) the structures all fall within page boundaries,
670 *       but a linear mapping is recommended.  Currently assumes that
671 *       the mapping will remain identical over time (which should be
672 *       OK since it only accesses memory which shouldn't be munged
673 *       by the OS anyway).
674 *   (2) : The OS only consumes memory which the BIOS says is OK to use,
675 *       and not any of the BIOS standard areas (the areas 0x400 to
676 *       0x600, the EBDA, 0xE0000 to 0xFFFFF, and unreported physical
677 *       RAM).  Sometimes a small amount of physical RAM is not
678 *       reported by the BIOS, to be used to store MPS and other
679 *       information.
680 *   (3) : It must be possible to read the CMOS.
681 *   (4) : There must be between 512K and 640K of lower memory (this is a
682 *       sanity check).
683 *
684 *  Function finished.
685 */
686static int
687imps_probe(void)
688{
689  /*
690   *  Determine possible address of the EBDA
691   */
692  unsigned ebda_addr = *((unsigned short *)
693             PHYS_TO_VIRTUAL(EBDA_SEG_ADDR)) << 4;
694
695  /*
696   *  Determine amount of installed lower memory (not *available*
697   *  lower memory).
698   *
699   *  NOTE:  This should work reliably as long as we verify the
700   *         machine is at least a system that could possibly have
701   *         MPS compatibility to begin with.
702   */
703  unsigned mem_lower = ((CMOS_READ_BYTE(CMOS_BASE_MEMORY+1) << 8)
704            | CMOS_READ_BYTE(CMOS_BASE_MEMORY))       << 10;
705
706#ifdef IMPS_DEBUG
707  imps_enabled = 0;
708  imps_num_cpus = 1;
709#endif
710
711  /*
712   *  Sanity check : if this isn't reasonable, it is almost impossibly
713   *    unlikely to be an MPS compatible machine, so return failure.
714   */
715  if (mem_lower < 512*1024 || mem_lower > 640*1024) {
716    return 0;
717  }
718
719  if (ebda_addr > mem_lower - 1024
720   || ebda_addr + *((unsigned char *) PHYS_TO_VIRTUAL(ebda_addr))
721         * 1024 > mem_lower) {
722    ebda_addr = 0;
723  }
724
725  if (((ebda_addr && imps_scan(ebda_addr, 1024))
726   || (!ebda_addr && imps_scan(mem_lower - 1024, 1024))
727   || imps_scan(0xF0000, 0x10000)) && imps_enabled) {
728    return imps_num_cpus;
729  }
730
731  /*
732   *  If no BIOS info on MPS hardware is found, then return failure.
733   */
734
735  return 0;
736}
737
738/*
739 *  RTEMS SMP BSP Support
740 */
741static void smp_apic_ack(void)
742{
743  (void) IMPS_LAPIC_READ(LAPIC_SPIV);  /* dummy read */
744  IMPS_LAPIC_WRITE(LAPIC_EOI, 0 );     /* ACK the interrupt */
745}
746
747static void bsp_inter_processor_interrupt(void *arg)
748{
749  (void) arg;
750
751  smp_apic_ack();
752
753  _SMP_Inter_processor_interrupt_handler();
754}
755
756static void ipi_install_irq(void)
757{
758  rtems_status_code status;
759
760  status = rtems_interrupt_handler_install(
761    16,
762    "smp-imps",
763    RTEMS_INTERRUPT_UNIQUE,
764    bsp_inter_processor_interrupt,
765    NULL
766  );
767  assert(status == RTEMS_SUCCESSFUL);
768}
769
770#ifdef __SSE__
771extern void enable_sse(void);
772#endif
773
774/* pc386 specific initialization */
775static void secondary_cpu_initialize(void)
776{
777  int apicid;
778
779  asm volatile( "lidt IDT_Descriptor" );
780
781  apicid = IMPS_LAPIC_READ(LAPIC_SPIV);
782  IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC);
783
784#ifdef __SSE__
785  enable_sse();
786#endif
787
788  _SMP_Start_multitasking_on_secondary_processor();
789}
790
791uint32_t _CPU_SMP_Initialize( void )
792{
793  /* XXX need to deal with finding too many cores */
794
795  return (uint32_t) imps_probe();
796}
797
798bool _CPU_SMP_Start_processor( uint32_t cpu_index )
799{
800  (void) cpu_index;
801
802  return true;
803}
804
805void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
806{
807  if ( cpu_count > 1 )
808    ipi_install_irq();
809}
810
811void _CPU_SMP_Send_interrupt( uint32_t target_processor_index )
812{
813  send_ipi( target_processor_index, 0x30 );
814}
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