source: rtems/c/src/lib/libbsp/i386/shared/smp/smp-imps.c @ 2f6108f9

4.115
Last change on this file since 2f6108f9 was 2f6108f9, checked in by Sebastian Huber <sebastian.huber@…>, on May 28, 2013 at 8:58:19 AM

smp: Simplify SMP initialization sequence

Delete bsp_smp_wait_for(). Other parts of the system work without
timeout, e.g. the spinlocks. Using a timeout here does not make the
system more robust.

Delete bsp_smp_cpu_state and replace it with Per_CPU_State. The
Per_CPU_State follows the Score naming conventions. Add
_Per_CPU_Change_state() and _Per_CPU_Wait_for_state() functions to
change and observe states.

Use Per_CPU_State in Per_CPU_Control instead of the anonymous integer.

Add _CPU_Processor_event_broadcast() and _CPU_Processor_event_receive()
functions provided by the CPU port. Use these functions in
_Per_CPU_Change_state() and _Per_CPU_Wait_for_state().

Add prototype for _SMP_Send_message().

Delete RTEMS_BSP_SMP_FIRST_TASK message. The first context switch is
now performed in rtems_smp_secondary_cpu_initialize(). Issuing the
first context switch in the context of the inter-processor interrupt is
not possible on systems with a modern interrupt controller. Such an
interrupt controler usually requires a handshake protocol with interrupt
acknowledge and end of interrupt signals. A direct context switch in an
interrupt handler circumvents the interrupt processing epilogue and may
leave the system in an inconsistent state.

Release lock in rtems_smp_process_interrupt() even if no message was
delivered. This prevents deadlock of the system.

Simplify and format _SMP_Send_message(),
_SMP_Request_other_cores_to_perform_first_context_switch(),
_SMP_Request_other_cores_to_dispatch() and
_SMP_Request_other_cores_to_shutdown().

  • Property mode set to 100644
File size: 21.6 KB
Line 
1/*
2 * Author: Erich Boleyn  <erich@uruk.org>
3 *         http://www.uruk.org/~erich/
4 *
5 * Copyright (c) 1997-2011 Erich Boleyn.  All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 *    derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30/*
31 *  Source file implementing Intel MultiProcessor Specification (MPS)
32 *  version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs,
33 *  with hooks for running correctly on a standard PC without the hardware.
34 *
35 *  This file was created from information in the Intel MPS version 1.4
36 *  document, order number 242016-004, which can be ordered from the
37 *  Intel literature center.
38 *
39 *  General limitations of this code:
40 *
41 *   (1) : This code has never been tested on an MPS-compatible system with
42 *           486 CPUs, but is expected to work.
43 *   (2) : Presumes "int", "long", and "unsigned" are 32 bits in size, and
44 *       that 32-bit pointers and memory addressing is used uniformly.
45 */
46
47#define _SMP_IMPS_C
48
49/*
50 *  Includes here
51 */
52#if 0
53#define IMPS_DEBUG
54#endif
55
56#include <bsp/apic.h>
57#include <bsp/smp-imps.h>
58
59/*
60 *  XXXXX  The following absolutely must be defined!!!
61 *
62 *  The "KERNEL_PRINT" could be made a null macro with no danger, of
63 *  course, but pretty much nothing would work without the other
64 *  ones defined.
65 */
66
67#if 0
68#define KERNEL_PRINT(x)       /* some kind of print function */
69#define CMOS_WRITE_BYTE(x,y)  /* write unsigned char "y" at CMOS loc "x" */
70#define CMOS_READ_BYTE(x)     /* read unsigned char at CMOS loc "x" */
71#define PHYS_TO_VIRTUAL(x)    /* convert physical address "x" to virtual */
72#define VIRTUAL_TO_PHYS(x)    /* convert virtual address "x" to physical */
73#define UDELAY(x)             /* delay roughly at least "x" microsecs */
74#define READ_MSR_LO(x)        /* Read MSR low function */
75#else
76#include <string.h>
77#include <unistd.h>
78#include <rtems.h>
79#include <rtems/bspsmp.h>
80#include <rtems/bspIo.h>
81#include <libcpu/cpu.h>
82
83extern void _pc386_delay(void);
84
85/* #define KERNEL_PRINT(_format)       printk(_format) */
86
87static void CMOS_WRITE_BYTE(
88  unsigned int  offset,
89  unsigned char value
90)
91{
92  if ( offset < 128 ) {
93    outport_byte( 0x70, offset );
94    outport_byte( 0x71, value );
95  } else {
96    outport_byte( 0x72, offset );
97    outport_byte( 0x73, value );
98  }
99}
100
101static unsigned char CMOS_READ_BYTE(
102  unsigned int  offset
103)
104{
105  unsigned char value;
106  if ( offset < 128 ) {
107    outport_byte( 0x70, offset );
108    inport_byte( 0x71, value );
109  } else {
110    outport_byte( 0x72, offset );
111    inport_byte( 0x73, value );
112  }
113  return value;
114}
115
116#define PHYS_TO_VIRTUAL(_x)    _x
117#define VIRTUAL_TO_PHYS(_x)    _x
118static void UDELAY(int x)
119{ int _i = x;
120  while ( _i-- )
121    _pc386_delay();
122}
123 
124#define READ_MSR_LO(_x) \
125  (unsigned int)(read_msr(_x) & 0xffffffff)
126
127static inline unsigned long long read_msr(unsigned int msr)
128{
129  unsigned long long value;
130 
131  asm volatile("rdmsr" : "=A" (value) : "c" (msr));
132  return value;
133}
134#endif
135
136/*
137 *  Defines that are here so as not to be in the global header file.
138 */
139#define EBDA_SEG_ADDR       0x40E
140#define BIOS_RESET_VECTOR   0x467
141#define LAPIC_ADDR_DEFAULT  0xFEE00000uL
142#define IOAPIC_ADDR_DEFAULT 0xFEC00000uL
143#define CMOS_RESET_CODE     0xF
144#define CMOS_RESET_JUMP     0xa
145#define CMOS_BASE_MEMORY    0x15
146
147/*
148 *  Static defines here for SMP use.
149 */
150
151#define DEF_ENTRIES  23
152
153static struct {
154  imps_processor proc[2];
155  imps_bus bus[2];
156  imps_ioapic ioapic;
157  imps_interrupt intin[16];
158  imps_interrupt lintin[2];
159} defconfig = {
160  { { IMPS_BCT_PROCESSOR, 0, 0, 0, 0, 0},
161    { IMPS_BCT_PROCESSOR, 1, 0, 0, 0, 0} },
162  { { IMPS_BCT_BUS, 0, {'E', 'I', 'S', 'A', ' ', ' '}},
163    { 255, 1, {'P', 'C', 'I', ' ', ' ', ' '}} },
164  { IMPS_BCT_IOAPIC, 0, 0, IMPS_FLAG_ENABLED, IOAPIC_ADDR_DEFAULT },
165  { { IMPS_BCT_IO_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 0, 0xFF, 0},
166    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 1, 0xFF, 1},
167    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 0, 0xFF, 2},
168    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 3, 0xFF, 3},
169    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 4, 0xFF, 4},
170    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 5, 0xFF, 5},
171    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 6, 0xFF, 6},
172    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 7, 0xFF, 7},
173    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 8, 0xFF, 8},
174    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 9, 0xFF, 9},
175    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 10, 0xFF, 10},
176    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 11, 0xFF, 11},
177    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 12, 0xFF, 12},
178    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 13, 0xFF, 13},
179    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 14, 0xFF, 14},
180    { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 15, 0xFF, 15} },
181  { { IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 15, 0xFF, 0},
182    { IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_NMI, 0, 0, 15, 0xFF, 1} }
183};
184
185/*
186 *  Exported globals here.
187 */
188
189volatile int imps_release_cpus = 0;
190int imps_enabled = 0;
191int imps_num_cpus = 1;
192unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS];
193unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS];
194
195/* now defined in getcpuid.c */
196extern unsigned imps_lapic_addr;
197
198static void secondary_cpu_initialize(void);
199
200/*
201 *  MPS checksum function
202 *
203 *  Function finished.
204 */
205static int
206get_checksum(unsigned start, int length)
207{
208  unsigned sum = 0;
209
210  while (length-- > 0) {
211    sum += *((unsigned char *) (start++));
212  }
213
214  return (sum&0xFF);
215}
216
217/*
218 *  APIC ICR write and status check function.
219 */
220static int
221send_ipi(unsigned int dst, unsigned int v)
222{
223  int to, send_status;
224
225  IMPS_LAPIC_WRITE(LAPIC_ICR+0x10, (dst << 24));
226  IMPS_LAPIC_WRITE(LAPIC_ICR, v);
227
228  /* Wait for send to finish */
229  to = 0;
230  do {
231    UDELAY(100);
232    send_status = IMPS_LAPIC_READ(LAPIC_ICR) & LAPIC_ICR_STATUS_PEND;
233  } while (send_status && (to++ < 1000));
234
235  return (to < 1000);
236}
237
238/*
239 *  Primary function for booting individual CPUs.
240 *
241 *  This must be modified to perform whatever OS-specific initialization
242 *  that is required.
243 */
244int
245boot_cpu(imps_processor *proc)
246{
247  int apicid = proc->apic_id, success = 1;
248  unsigned bootaddr, accept_status;
249  unsigned bios_reset_vector = PHYS_TO_VIRTUAL(BIOS_RESET_VECTOR);
250
251  /*
252   * Copy boot code for secondary CPUs here.  Find it in between
253   * "patch_code_start" and "patch_code_end" symbols.  The other CPUs
254   * will start there in 16-bit real mode under the 1MB boundary.
255   * "patch_code_start" should be placed at a 4K-aligned address
256   * under the 1MB boundary.
257   */
258
259  uint32_t *reset;
260
261  bootaddr = (512-64)*1024;
262  reset= (uint32_t *)bootaddr;
263
264  memcpy(
265    (char *) bootaddr,
266    _binary_appstart_bin_start,
267    (size_t)_binary_appstart_bin_size
268  );
269
270  reset[1] = (uint32_t)secondary_cpu_initialize;
271  reset[2] = (uint32_t)_Per_CPU_Information[apicid].interrupt_stack_high;
272
273  /*
274   *  Generic CPU startup sequence starts here.
275   */
276
277  /* set BIOS reset vector */
278  CMOS_WRITE_BYTE(CMOS_RESET_CODE, CMOS_RESET_JUMP);
279  *((volatile unsigned *) bios_reset_vector) = ((bootaddr & 0xFF000) << 12);
280
281  /* clear the APIC error register */
282  IMPS_LAPIC_WRITE(LAPIC_ESR, 0);
283  accept_status = IMPS_LAPIC_READ(LAPIC_ESR);
284
285  /* assert INIT IPI */
286  send_ipi(
287    apicid,
288    LAPIC_ICR_TM_LEVEL | LAPIC_ICR_LEVELASSERT | LAPIC_ICR_DM_INIT
289  );
290  UDELAY(10000);
291
292  /* de-assert INIT IPI */
293  send_ipi(apicid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_DM_INIT);
294
295  UDELAY(10000);
296
297  /*
298   *  Send Startup IPIs if not an old pre-integrated APIC.
299   */
300
301  if (proc->apic_ver >= APIC_VER_NEW) {
302    int i;
303    for (i = 1; i <= 2; i++) {
304      send_ipi(apicid, LAPIC_ICR_DM_SIPI | ((bootaddr >> 12) & 0xFF));
305      UDELAY(1000);
306    }
307  }
308
309  /*
310   *  Generic CPU startup sequence ends here, the rest is cleanup.
311   */
312
313  /* clear the APIC error register */
314  IMPS_LAPIC_WRITE(LAPIC_ESR, 0);
315  accept_status = IMPS_LAPIC_READ(LAPIC_ESR);
316
317  /* clean up BIOS reset vector */
318  CMOS_WRITE_BYTE(CMOS_RESET_CODE, 0);
319  *((volatile unsigned *) bios_reset_vector) = 0;
320
321  printk("\n");
322
323  return success;
324}
325
326/*
327 *  read bios stuff and fill tables
328 */
329static void
330add_processor(imps_processor *proc)
331{
332  int apicid = proc->apic_id;
333
334  printk("  Processor [APIC id %d ver %d]: ", apicid, proc->apic_ver);
335  if (!(proc->flags & IMPS_FLAG_ENABLED)) {
336    printk("DISABLED\n");
337    return;
338  }
339  if (proc->flags & (IMPS_CPUFLAG_BOOT)) {
340    printk("#0  BootStrap Processor (BSP)\n");
341    return;
342  }
343  if (boot_cpu(proc)) {
344
345    /*  XXXXX  add OS-specific setup for secondary CPUs here */
346
347    imps_cpu_apic_map[imps_num_cpus] = apicid;
348    imps_apic_cpu_map[apicid] = imps_num_cpus;
349    imps_num_cpus++;
350  }
351}
352
353
354static void
355add_bus(imps_bus *bus)
356{
357  char str[8];
358
359  memcpy(str, bus->bus_type, 6);
360  str[6] = 0;
361  printk("  Bus id %d is %s\n", bus->id, str);
362
363  /*  XXXXX  add OS-specific code here */
364}
365
366static void
367add_ioapic(imps_ioapic *ioapic)
368{
369  printk("  I/O APIC id %d ver %d, address: 0x%x  ",
370          ioapic->id, ioapic->ver, ioapic->addr);
371  if (!(ioapic->flags & IMPS_FLAG_ENABLED)) {
372    printk("DISABLED\n");
373    return;
374  }
375  printk("\n");
376
377  /*  XXXXX  add OS-specific code here */
378}
379
380static void
381imps_read_config_table(unsigned start, int count)
382{
383  while (count-- > 0) {
384    switch (*((unsigned char *)start)) {
385    case IMPS_BCT_PROCESSOR:
386      if ( imps_num_cpus < rtems_configuration_get_maximum_processors() ) {
387        add_processor((imps_processor *)start);
388      } else 
389        imps_num_cpus++;
390      start += 12;  /* 20 total */
391      break;
392    case IMPS_BCT_BUS:
393      add_bus((imps_bus *)start);
394      break;
395    case IMPS_BCT_IOAPIC:
396      add_ioapic((imps_ioapic *)start);
397      break;
398#if 0  /*  XXXXX  uncomment this if "add_io_interrupt" is implemented */
399    case IMPS_BCT_IO_INTERRUPT:
400      add_io_interrupt((imps_interrupt *)start);
401      break;
402#endif
403#if 0  /*  XXXXX  uncomment this if "add_local_interrupt" is implemented */
404    case IMPS_BCT_LOCAL_INTERRUPT:
405      add_local_interupt((imps_interrupt *)start);
406      break;
407#endif
408    default:
409      break;
410    }
411    start += 8;
412  }
413  if ( imps_num_cpus > rtems_configuration_get_maximum_processors() ) {
414    printk(
415      "WARNING!! Found more CPUs (%d) than configured for (%d)!!\n",
416      imps_num_cpus - 1,
417      rtems_configuration_get_maximum_processors()
418    );
419    imps_num_cpus = rtems_configuration_get_maximum_processors();
420    return;
421  }
422}
423
424static int
425imps_bad_bios(imps_fps *fps_ptr)
426{
427  int sum;
428  imps_cth *local_cth_ptr
429    = (imps_cth *) PHYS_TO_VIRTUAL(fps_ptr->cth_ptr);
430
431  if (fps_ptr->feature_info[0] > IMPS_FPS_DEFAULT_MAX) {
432    printk("    Invalid MP System Configuration type %d\n",
433            fps_ptr->feature_info[0]);
434    return 1;
435  }
436
437  if (fps_ptr->cth_ptr) {
438    sum = get_checksum((unsigned)local_cth_ptr,
439                                   local_cth_ptr->base_length);
440    if (local_cth_ptr->sig != IMPS_CTH_SIGNATURE || sum) {
441      printk(
442        "    Bad MP Config Table sig 0x%x and/or checksum 0x%x\n",
443        (unsigned)(fps_ptr->cth_ptr),
444        sum
445      );
446      return 1;
447    }
448    if (local_cth_ptr->spec_rev != fps_ptr->spec_rev) {
449      printk(
450        "    Bad MP Config Table sub-revision # %d\n",
451        local_cth_ptr->spec_rev
452      );
453      return 1;
454    }
455    if (local_cth_ptr->extended_length) {
456      sum = (get_checksum(((unsigned)local_cth_ptr)
457              + local_cth_ptr->base_length,
458              local_cth_ptr->extended_length)
459             + local_cth_ptr->extended_checksum) & 0xFF;
460      if (sum) {
461        printk("    Bad Extended MP Config Table checksum 0x%x\n", sum);
462        return 1;
463      }
464    }
465  } else if (!fps_ptr->feature_info[0]) {
466    printk("    Missing configuration information\n");
467    return 1;
468  }
469
470  return 0;
471}
472
473static void
474imps_read_bios(imps_fps *fps_ptr)
475{
476  int apicid;
477  unsigned cth_start, cth_count;
478  imps_cth *local_cth_ptr
479    = (imps_cth *)PHYS_TO_VIRTUAL(fps_ptr->cth_ptr);
480  char *str_ptr;
481
482  printk("Intel MultiProcessor Spec 1.%d BIOS support detected\n",
483          fps_ptr->spec_rev);
484
485  /*
486   *  Do all checking of errors which would definitely
487   *  lead to failure of the SMP boot here.
488   */
489  if (imps_bad_bios(fps_ptr)) {
490    printk("    Disabling MPS support\n");
491    return;
492  }
493
494  if (fps_ptr->feature_info[1] & IMPS_FPS_IMCRP_BIT) {
495    str_ptr = "IMCR and PIC";
496  } else {
497    str_ptr = "Virtual Wire";
498  }
499  if (fps_ptr->cth_ptr) {
500    imps_lapic_addr = local_cth_ptr->lapic_addr;
501  } else {
502    imps_lapic_addr = LAPIC_ADDR_DEFAULT;
503  }
504  printk("    APIC config: \"%s mode\"    Local APIC address: 0x%x\n",
505          str_ptr, imps_lapic_addr);
506  if (imps_lapic_addr != (READ_MSR_LO(0x1b) & 0xFFFFF000)) {
507    printk("Inconsistent Local APIC address, Disabling SMP support\n");
508    return;
509  }
510  imps_lapic_addr = PHYS_TO_VIRTUAL(imps_lapic_addr);
511
512  /*
513   *  Setup primary CPU.
514   */
515  apicid = IMPS_LAPIC_READ(LAPIC_SPIV);
516  IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC);
517  apicid = APIC_ID(IMPS_LAPIC_READ(LAPIC_ID));
518  imps_cpu_apic_map[0] = apicid;
519  imps_apic_cpu_map[apicid] = 0;
520
521  if (fps_ptr->cth_ptr) {
522    char str1[16], str2[16];
523    memcpy(str1, local_cth_ptr->oem_id, 8);
524    str1[8] = 0;
525    memcpy(str2, local_cth_ptr->prod_id, 12);
526    str2[12] = 0;
527    printk("  OEM id: %s  Product id: %s\n", str1, str2);
528    cth_start = ((unsigned) local_cth_ptr) + sizeof(imps_cth);
529    cth_count = local_cth_ptr->entry_count;
530  } else {
531    *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) =  IOAPIC_ID;
532    defconfig.ioapic.id
533      = APIC_ID(*((volatile unsigned *)
534            (IOAPIC_ADDR_DEFAULT+IOAPIC_RW)));
535    *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) =  IOAPIC_VER;
536    defconfig.ioapic.ver
537      = APIC_VERSION(*((volatile unsigned *)
538           (IOAPIC_ADDR_DEFAULT+IOAPIC_RW)));
539    defconfig.proc[apicid].flags
540      = IMPS_FLAG_ENABLED|IMPS_CPUFLAG_BOOT;
541    defconfig.proc[!apicid].flags = IMPS_FLAG_ENABLED;
542    imps_num_cpus = 2;
543    if (fps_ptr->feature_info[0] == 1
544     || fps_ptr->feature_info[0] == 5) {
545      memcpy(defconfig.bus[0].bus_type, "ISA   ", 6);
546    }
547    if (fps_ptr->feature_info[0] == 4
548     || fps_ptr->feature_info[0] == 7) {
549      memcpy(defconfig.bus[0].bus_type, "MCA   ", 6);
550    }
551    if (fps_ptr->feature_info[0] > 4) {
552      defconfig.proc[0].apic_ver = 0x10;
553      defconfig.proc[1].apic_ver = 0x10;
554      defconfig.bus[1].type = IMPS_BCT_BUS;
555    }
556    if (fps_ptr->feature_info[0] == 2) {
557      defconfig.intin[2].type = 255;
558      defconfig.intin[13].type = 255;
559    }
560    if (fps_ptr->feature_info[0] == 7) {
561      defconfig.intin[0].type = 255;
562    }
563    cth_start = (unsigned) &defconfig;
564    cth_count = DEF_ENTRIES;
565  }
566  imps_read_config_table(cth_start, cth_count);
567
568  /* %%%%% ESB read extended entries here */
569
570  imps_enabled = 1;
571}
572
573/*
574 *  Given a region to check, this actually looks for the "MP Floating
575 *  Pointer Structure".  The return value indicates if the correct
576 *  signature and checksum for a floating pointer structure of the
577 *  appropriate spec revision was found.  If so, then do not search
578 *  further.
579 *
580 *  NOTE:  The memory scan will always be in the bottom 1 MB.
581 *
582 *  This function presumes that "start" will always be aligned to a 16-bit
583 *  boundary.
584 *
585 *  Function finished.
586 */
587static int
588imps_scan(unsigned start, unsigned length)
589{
590  printk("Scanning from 0x%x for %d bytes\n", start, length);
591
592  while (length > 0) {
593    imps_fps *fps_ptr = (imps_fps *) PHYS_TO_VIRTUAL(start);
594
595    if (fps_ptr->sig == IMPS_FPS_SIGNATURE
596     && fps_ptr->length == 1
597     && (fps_ptr->spec_rev == 1 || fps_ptr->spec_rev == 4)
598     && !get_checksum(start, 16)) {
599      printk("Found MP Floating Structure Pointer at %x\n", start);
600      imps_read_bios(fps_ptr);
601      return 1;
602    }
603
604    length -= 16;
605    start += 16;
606  }
607
608  return 0;
609}
610
611#if !defined(__rtems__)
612/*
613 *  This is the primary function to "force" SMP support, with
614 *  the assumption that you have consecutively numbered APIC ids.
615 */
616int
617imps_force(int ncpus)
618{
619  int apicid, i;
620  imps_processor p;
621
622  printk("Intel MultiProcessor \"Force\" Support\n");
623
624  imps_lapic_addr = (READ_MSR_LO(0x1b) & 0xFFFFF000);
625  imps_lapic_addr = PHYS_TO_VIRTUAL(imps_lapic_addr);
626
627  /*
628   *  Setup primary CPU.
629   */
630  apicid = IMPS_LAPIC_READ(LAPIC_SPIV);
631  IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC);
632  apicid = APIC_ID(IMPS_LAPIC_READ(LAPIC_ID));
633  imps_cpu_apic_map[0] = apicid;
634  imps_apic_cpu_map[apicid] = 0;
635
636  p.type = 0;
637  p.apic_ver = 0x10;
638  p.signature = p.features = 0;
639
640  for (i = 0; i < ncpus; i++) {
641    if (apicid == i) {
642      p.flags = IMPS_FLAG_ENABLED | IMPS_CPUFLAG_BOOT;
643    } else {
644      p.flags = IMPS_FLAG_ENABLED;
645    }
646    p.apic_id = i;
647    add_processor(&p);
648  }
649
650  return imps_num_cpus;
651}
652#endif
653
654/*
655 *  This is the primary function for probing for MPS compatible hardware
656 *  and BIOS information.  Call this during the early stages of OS startup,
657 *  before memory can be messed up.
658 *
659 *  The probe looks for the "MP Floating Pointer Structure" at locations
660 *  listed at the top of page 4-2 of the spec.
661 *
662 *  Environment requirements from the OS to run:
663 *
664 *   (1) : A non-linear virtual to physical memory mapping is probably OK,
665 *       as (I think) the structures all fall within page boundaries,
666 *       but a linear mapping is recommended.  Currently assumes that
667 *       the mapping will remain identical over time (which should be
668 *       OK since it only accesses memory which shouldn't be munged
669 *       by the OS anyway).
670 *   (2) : The OS only consumes memory which the BIOS says is OK to use,
671 *       and not any of the BIOS standard areas (the areas 0x400 to
672 *       0x600, the EBDA, 0xE0000 to 0xFFFFF, and unreported physical
673 *       RAM).  Sometimes a small amount of physical RAM is not
674 *       reported by the BIOS, to be used to store MPS and other
675 *       information.
676 *   (3) : It must be possible to read the CMOS.
677 *   (4) : There must be between 512K and 640K of lower memory (this is a
678 *       sanity check).
679 *
680 *  Function finished.
681 */
682int
683imps_probe(void)
684{
685  /*
686   *  Determine possible address of the EBDA
687   */
688  unsigned ebda_addr = *((unsigned short *)
689             PHYS_TO_VIRTUAL(EBDA_SEG_ADDR)) << 4;
690
691  /*
692   *  Determine amount of installed lower memory (not *available*
693   *  lower memory).
694   *
695   *  NOTE:  This should work reliably as long as we verify the
696   *         machine is at least a system that could possibly have
697   *         MPS compatibility to begin with.
698   */
699  unsigned mem_lower = ((CMOS_READ_BYTE(CMOS_BASE_MEMORY+1) << 8)
700            | CMOS_READ_BYTE(CMOS_BASE_MEMORY))       << 10;
701
702#ifdef IMPS_DEBUG
703  imps_enabled = 0;
704  imps_num_cpus = 1;
705#endif
706
707  /*
708   *  Sanity check : if this isn't reasonable, it is almost impossibly
709   *    unlikely to be an MPS compatible machine, so return failure.
710   */
711  if (mem_lower < 512*1024 || mem_lower > 640*1024) {
712    return 0;
713  }
714
715  if (ebda_addr > mem_lower - 1024
716   || ebda_addr + *((unsigned char *) PHYS_TO_VIRTUAL(ebda_addr))
717         * 1024 > mem_lower) {
718    ebda_addr = 0;
719  }
720
721  if (((ebda_addr && imps_scan(ebda_addr, 1024))
722   || (!ebda_addr && imps_scan(mem_lower - 1024, 1024))
723   || imps_scan(0xF0000, 0x10000)) && imps_enabled) {
724    return imps_num_cpus;
725  }
726
727  /*
728   *  If no BIOS info on MPS hardware is found, then return failure.
729   */
730
731  return 0;
732}
733
734/*
735 *  RTEMS SMP BSP Support
736 */
737void smp_apic_ack(void)
738{
739  (void) IMPS_LAPIC_READ(LAPIC_SPIV);  /* dummy read */
740  IMPS_LAPIC_WRITE(LAPIC_EOI, 0 );     /* ACK the interrupt */
741}
742
743rtems_isr ap_ipi_isr(
744  rtems_vector_number vector
745)
746{
747  smp_apic_ack();
748
749  rtems_smp_process_interrupt();
750}
751
752#include <rtems/irq.h>
753
754static rtems_irq_connect_data apIPIIrqData = {
755  16,
756  (void *)ap_ipi_isr,
757  0,
758  NULL,            /* On */
759  NULL,            /* Off */
760  NULL,            /* IsOn */
761};
762
763extern void bsp_reset(void);
764void ipi_install_irq(void)
765{
766  if (!BSP_install_rtems_irq_handler (&apIPIIrqData)) {
767    printk("Unable to initialize IPI\n");
768    bsp_reset();
769  }
770}
771
772#ifdef __SSE__
773extern void enable_sse(void);
774#endif
775
776/* pc386 specific initialization */
777static void secondary_cpu_initialize(void)
778{
779  int apicid;
780
781  asm volatile( "lidt IDT_Descriptor" );
782
783  apicid = IMPS_LAPIC_READ(LAPIC_SPIV);
784  IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC);
785
786#ifdef __SSE__
787  enable_sse();
788#endif
789
790  rtems_smp_secondary_cpu_initialize();
791}
792
793#include <rtems/bspsmp.h>
794uint32_t bsp_smp_initialize( uint32_t configured_cpu_count )
795{
796  int cores;
797  /* XXX need to deal with finding too many cores */
798
799  cores = imps_probe();
800
801  if ( cores > 1 )
802    ipi_install_irq();
803  return cores;
804}
805
806void bsp_smp_interrupt_cpu(
807  int cpu
808)
809{
810  send_ipi( cpu, 0x30 );
811}
812
813void bsp_smp_broadcast_interrupt(void)
814{
815  /* Single broadcast interrupt */
816  send_ipi( 0, LAPIC_ICR_DS_ALLEX | 0x30 );
817}
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