1 | /* |
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2 | * Author: Erich Boleyn <erich@uruk.org> |
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3 | * http://www.uruk.org/~erich/ |
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4 | * |
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5 | * Copyright (c) 1997-2011 Erich Boleyn. All rights reserved. |
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6 | * |
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7 | * Redistribution and use in source and binary forms, with or without |
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8 | * modification, are permitted provided that the following conditions |
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9 | * are met: |
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10 | * 1. Redistributions of source code must retain the above copyright |
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11 | * notice, this list of conditions and the following disclaimer. |
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12 | * 2. Redistributions in binary form must reproduce the above copyright |
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13 | * notice, this list of conditions and the following disclaimer in the |
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14 | * documentation and/or other materials provided with the distribution. |
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15 | * 3. The name of the author may not be used to endorse or promote products |
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16 | * derived from this software without specific prior written permission. |
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17 | * |
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18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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20 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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21 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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22 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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23 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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24 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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25 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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26 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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27 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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28 | */ |
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29 | |
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30 | /* |
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31 | * Source file implementing Intel MultiProcessor Specification (MPS) |
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32 | * version 1.1 and 1.4 SMP hardware control for Intel Architecture CPUs, |
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33 | * with hooks for running correctly on a standard PC without the hardware. |
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34 | * |
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35 | * This file was created from information in the Intel MPS version 1.4 |
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36 | * document, order number 242016-004, which can be ordered from the |
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37 | * Intel literature center. |
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38 | * |
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39 | * General limitations of this code: |
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40 | * |
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41 | * (1) : This code has never been tested on an MPS-compatible system with |
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42 | * 486 CPUs, but is expected to work. |
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43 | * (2) : Presumes "int", "long", and "unsigned" are 32 bits in size, and |
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44 | * that 32-bit pointers and memory addressing is used uniformly. |
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45 | */ |
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46 | |
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47 | #define _SMP_IMPS_C |
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48 | |
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49 | /* |
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50 | * Includes here |
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51 | */ |
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52 | #if 0 |
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53 | #define IMPS_DEBUG |
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54 | #endif |
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55 | |
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56 | #include <bsp/apic.h> |
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57 | #include <bsp/smp-imps.h> |
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58 | |
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59 | /* |
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60 | * XXXXX The following absolutely must be defined!!! |
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61 | * |
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62 | * The "KERNEL_PRINT" could be made a null macro with no danger, of |
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63 | * course, but pretty much nothing would work without the other |
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64 | * ones defined. |
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65 | */ |
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66 | |
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67 | #if 0 |
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68 | #define KERNEL_PRINT(x) /* some kind of print function */ |
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69 | #define CMOS_WRITE_BYTE(x,y) /* write unsigned char "y" at CMOS loc "x" */ |
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70 | #define CMOS_READ_BYTE(x) /* read unsigned char at CMOS loc "x" */ |
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71 | #define PHYS_TO_VIRTUAL(x) /* convert physical address "x" to virtual */ |
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72 | #define VIRTUAL_TO_PHYS(x) /* convert virtual address "x" to physical */ |
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73 | #define UDELAY(x) /* delay roughly at least "x" microsecs */ |
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74 | #define TEST_BOOTED(x) /* test bootaddr x to see if CPU started */ |
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75 | #define READ_MSR_LO(x) /* Read MSR low function */ |
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76 | #else |
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77 | #include <string.h> |
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78 | #include <unistd.h> |
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79 | #include <rtems.h> |
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80 | #include <rtems/bspsmp.h> |
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81 | #include <rtems/bspIo.h> |
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82 | #include <libcpu/cpu.h> |
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83 | |
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84 | extern void _pc386_delay(void); |
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85 | |
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86 | /* #define KERNEL_PRINT(_format) printk(_format) */ |
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87 | |
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88 | static void CMOS_WRITE_BYTE( |
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89 | unsigned int offset, |
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90 | unsigned char value |
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91 | ) |
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92 | { |
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93 | if ( offset < 128 ) { |
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94 | outport_byte( 0x70, offset ); |
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95 | outport_byte( 0x71, value ); |
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96 | } else { |
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97 | outport_byte( 0x72, offset ); |
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98 | outport_byte( 0x73, value ); |
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99 | } |
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100 | } |
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101 | |
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102 | static unsigned char CMOS_READ_BYTE( |
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103 | unsigned int offset |
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104 | ) |
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105 | { |
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106 | unsigned char value; |
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107 | if ( offset < 128 ) { |
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108 | outport_byte( 0x70, offset ); |
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109 | inport_byte( 0x71, value ); |
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110 | } else { |
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111 | outport_byte( 0x72, offset ); |
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112 | inport_byte( 0x73, value ); |
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113 | } |
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114 | return value; |
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115 | } |
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116 | |
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117 | #define PHYS_TO_VIRTUAL(_x) _x |
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118 | #define VIRTUAL_TO_PHYS(_x) _x |
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119 | static void UDELAY(int x) |
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120 | { int _i = x; |
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121 | while ( _i-- ) |
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122 | _pc386_delay(); |
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123 | } |
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124 | |
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125 | #define READ_MSR_LO(_x) \ |
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126 | (unsigned int)(read_msr(_x) & 0xffffffff) |
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127 | |
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128 | #define TEST_BOOTED(_cpu) \ |
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129 | (_Per_CPU_Information[_cpu].state == RTEMS_BSP_SMP_CPU_INITIALIZED) |
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130 | |
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131 | static inline unsigned long long read_msr(unsigned int msr) |
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132 | { |
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133 | unsigned long long value; |
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134 | |
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135 | asm volatile("rdmsr" : "=A" (value) : "c" (msr)); |
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136 | return value; |
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137 | } |
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138 | #endif |
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139 | |
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140 | /* |
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141 | * Defines that are here so as not to be in the global header file. |
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142 | */ |
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143 | #define EBDA_SEG_ADDR 0x40E |
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144 | #define BIOS_RESET_VECTOR 0x467 |
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145 | #define LAPIC_ADDR_DEFAULT 0xFEE00000uL |
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146 | #define IOAPIC_ADDR_DEFAULT 0xFEC00000uL |
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147 | #define CMOS_RESET_CODE 0xF |
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148 | #define CMOS_RESET_JUMP 0xa |
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149 | #define CMOS_BASE_MEMORY 0x15 |
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150 | |
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151 | /* |
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152 | * Static defines here for SMP use. |
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153 | */ |
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154 | |
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155 | #define DEF_ENTRIES 23 |
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156 | |
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157 | static struct { |
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158 | imps_processor proc[2]; |
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159 | imps_bus bus[2]; |
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160 | imps_ioapic ioapic; |
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161 | imps_interrupt intin[16]; |
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162 | imps_interrupt lintin[2]; |
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163 | } defconfig = { |
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164 | { { IMPS_BCT_PROCESSOR, 0, 0, 0, 0, 0}, |
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165 | { IMPS_BCT_PROCESSOR, 1, 0, 0, 0, 0} }, |
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166 | { { IMPS_BCT_BUS, 0, {'E', 'I', 'S', 'A', ' ', ' '}}, |
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167 | { 255, 1, {'P', 'C', 'I', ' ', ' ', ' '}} }, |
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168 | { IMPS_BCT_IOAPIC, 0, 0, IMPS_FLAG_ENABLED, IOAPIC_ADDR_DEFAULT }, |
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169 | { { IMPS_BCT_IO_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 0, 0xFF, 0}, |
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170 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 1, 0xFF, 1}, |
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171 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 0, 0xFF, 2}, |
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172 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 3, 0xFF, 3}, |
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173 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 4, 0xFF, 4}, |
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174 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 5, 0xFF, 5}, |
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175 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 6, 0xFF, 6}, |
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176 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 7, 0xFF, 7}, |
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177 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 8, 0xFF, 8}, |
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178 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 9, 0xFF, 9}, |
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179 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 10, 0xFF, 10}, |
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180 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 11, 0xFF, 11}, |
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181 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 12, 0xFF, 12}, |
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182 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 13, 0xFF, 13}, |
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183 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 14, 0xFF, 14}, |
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184 | { IMPS_BCT_IO_INTERRUPT, IMPS_INT_INT, 0, 0, 15, 0xFF, 15} }, |
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185 | { { IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_EXTINT, 0, 0, 15, 0xFF, 0}, |
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186 | { IMPS_BCT_LOCAL_INTERRUPT, IMPS_INT_NMI, 0, 0, 15, 0xFF, 1} } |
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187 | }; |
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188 | |
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189 | /* |
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190 | * Exported globals here. |
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191 | */ |
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192 | |
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193 | volatile int imps_release_cpus = 0; |
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194 | int imps_enabled = 0; |
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195 | int imps_num_cpus = 1; |
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196 | unsigned char imps_cpu_apic_map[IMPS_MAX_CPUS]; |
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197 | unsigned char imps_apic_cpu_map[IMPS_MAX_CPUS]; |
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198 | |
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199 | /* now defined in getcpuid.c */ |
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200 | extern unsigned imps_lapic_addr; |
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201 | |
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202 | /* |
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203 | * MPS checksum function |
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204 | * |
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205 | * Function finished. |
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206 | */ |
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207 | static int |
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208 | get_checksum(unsigned start, int length) |
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209 | { |
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210 | unsigned sum = 0; |
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211 | |
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212 | while (length-- > 0) { |
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213 | sum += *((unsigned char *) (start++)); |
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214 | } |
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215 | |
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216 | return (sum&0xFF); |
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217 | } |
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218 | |
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219 | /* |
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220 | * APIC ICR write and status check function. |
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221 | */ |
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222 | static int |
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223 | send_ipi(unsigned int dst, unsigned int v) |
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224 | { |
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225 | int to, send_status; |
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226 | |
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227 | IMPS_LAPIC_WRITE(LAPIC_ICR+0x10, (dst << 24)); |
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228 | IMPS_LAPIC_WRITE(LAPIC_ICR, v); |
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229 | |
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230 | /* Wait for send to finish */ |
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231 | to = 0; |
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232 | do { |
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233 | UDELAY(100); |
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234 | send_status = IMPS_LAPIC_READ(LAPIC_ICR) & LAPIC_ICR_STATUS_PEND; |
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235 | } while (send_status && (to++ < 1000)); |
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236 | |
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237 | return (to < 1000); |
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238 | } |
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239 | |
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240 | /* |
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241 | * Primary function for booting individual CPUs. |
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242 | * |
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243 | * This must be modified to perform whatever OS-specific initialization |
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244 | * that is required. |
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245 | */ |
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246 | int |
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247 | boot_cpu(imps_processor *proc) |
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248 | { |
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249 | int apicid = proc->apic_id, success = 1; |
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250 | unsigned bootaddr, accept_status; |
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251 | unsigned bios_reset_vector = PHYS_TO_VIRTUAL(BIOS_RESET_VECTOR); |
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252 | |
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253 | /* |
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254 | * Copy boot code for secondary CPUs here. Find it in between |
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255 | * "patch_code_start" and "patch_code_end" symbols. The other CPUs |
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256 | * will start there in 16-bit real mode under the 1MB boundary. |
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257 | * "patch_code_start" should be placed at a 4K-aligned address |
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258 | * under the 1MB boundary. |
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259 | */ |
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260 | |
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261 | uint32_t *reset; |
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262 | |
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263 | bootaddr = (512-64)*1024; |
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264 | reset= (uint32_t *)bootaddr; |
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265 | |
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266 | memcpy( |
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267 | (char *) bootaddr, |
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268 | _binary_appstart_bin_start, |
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269 | (size_t)_binary_appstart_bin_size |
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270 | ); |
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271 | |
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272 | reset[1] = (uint32_t)rtems_smp_secondary_cpu_initialize; |
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273 | reset[2] = (uint32_t)_Per_CPU_Information[apicid].interrupt_stack_high; |
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274 | |
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275 | /* |
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276 | * Generic CPU startup sequence starts here. |
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277 | */ |
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278 | |
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279 | /* set BIOS reset vector */ |
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280 | CMOS_WRITE_BYTE(CMOS_RESET_CODE, CMOS_RESET_JUMP); |
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281 | *((volatile unsigned *) bios_reset_vector) = ((bootaddr & 0xFF000) << 12); |
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282 | |
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283 | /* clear the APIC error register */ |
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284 | IMPS_LAPIC_WRITE(LAPIC_ESR, 0); |
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285 | accept_status = IMPS_LAPIC_READ(LAPIC_ESR); |
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286 | |
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287 | /* assert INIT IPI */ |
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288 | send_ipi( |
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289 | apicid, |
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290 | LAPIC_ICR_TM_LEVEL | LAPIC_ICR_LEVELASSERT | LAPIC_ICR_DM_INIT |
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291 | ); |
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292 | UDELAY(10000); |
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293 | |
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294 | /* de-assert INIT IPI */ |
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295 | send_ipi(apicid, LAPIC_ICR_TM_LEVEL | LAPIC_ICR_DM_INIT); |
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296 | |
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297 | UDELAY(10000); |
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298 | |
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299 | /* |
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300 | * Send Startup IPIs if not an old pre-integrated APIC. |
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301 | */ |
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302 | |
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303 | if (proc->apic_ver >= APIC_VER_NEW) { |
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304 | int i; |
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305 | for (i = 1; i <= 2; i++) { |
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306 | send_ipi(apicid, LAPIC_ICR_DM_SIPI | ((bootaddr >> 12) & 0xFF)); |
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307 | UDELAY(1000); |
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308 | } |
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309 | } |
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310 | |
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311 | /* |
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312 | * Check to see if other processor has started. |
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313 | */ |
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314 | bsp_smp_wait_for( |
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315 | (volatile unsigned int *)&_Per_CPU_Information[imps_num_cpus].state, |
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316 | RTEMS_BSP_SMP_CPU_INITIALIZED, |
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317 | 1600 |
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318 | ); |
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319 | if ( _Per_CPU_Information[imps_num_cpus].state == |
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320 | RTEMS_BSP_SMP_CPU_INITIALIZED ) |
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321 | printk("#%d Application Processor (AP)", imps_num_cpus); |
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322 | else { |
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323 | printk("CPU Not Responding, DISABLED"); |
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324 | success = 0; |
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325 | } |
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326 | |
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327 | /* |
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328 | * Generic CPU startup sequence ends here, the rest is cleanup. |
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329 | */ |
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330 | |
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331 | /* clear the APIC error register */ |
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332 | IMPS_LAPIC_WRITE(LAPIC_ESR, 0); |
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333 | accept_status = IMPS_LAPIC_READ(LAPIC_ESR); |
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334 | |
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335 | /* clean up BIOS reset vector */ |
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336 | CMOS_WRITE_BYTE(CMOS_RESET_CODE, 0); |
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337 | *((volatile unsigned *) bios_reset_vector) = 0; |
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338 | |
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339 | printk("\n"); |
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340 | |
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341 | return success; |
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342 | } |
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343 | |
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344 | /* |
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345 | * read bios stuff and fill tables |
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346 | */ |
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347 | static void |
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348 | add_processor(imps_processor *proc) |
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349 | { |
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350 | int apicid = proc->apic_id; |
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351 | |
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352 | printk(" Processor [APIC id %d ver %d]: ", apicid, proc->apic_ver); |
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353 | if (!(proc->flags & IMPS_FLAG_ENABLED)) { |
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354 | printk("DISABLED\n"); |
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355 | return; |
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356 | } |
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357 | if (proc->flags & (IMPS_CPUFLAG_BOOT)) { |
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358 | printk("#0 BootStrap Processor (BSP)\n"); |
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359 | return; |
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360 | } |
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361 | if (boot_cpu(proc)) { |
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362 | |
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363 | /* XXXXX add OS-specific setup for secondary CPUs here */ |
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364 | |
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365 | imps_cpu_apic_map[imps_num_cpus] = apicid; |
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366 | imps_apic_cpu_map[apicid] = imps_num_cpus; |
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367 | imps_num_cpus++; |
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368 | } |
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369 | } |
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370 | |
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371 | |
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372 | static void |
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373 | add_bus(imps_bus *bus) |
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374 | { |
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375 | char str[8]; |
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376 | |
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377 | memcpy(str, bus->bus_type, 6); |
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378 | str[6] = 0; |
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379 | printk(" Bus id %d is %s\n", bus->id, str); |
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380 | |
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381 | /* XXXXX add OS-specific code here */ |
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382 | } |
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383 | |
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384 | static void |
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385 | add_ioapic(imps_ioapic *ioapic) |
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386 | { |
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387 | printk(" I/O APIC id %d ver %d, address: 0x%x ", |
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388 | ioapic->id, ioapic->ver, ioapic->addr); |
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389 | if (!(ioapic->flags & IMPS_FLAG_ENABLED)) { |
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390 | printk("DISABLED\n"); |
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391 | return; |
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392 | } |
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393 | printk("\n"); |
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394 | |
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395 | /* XXXXX add OS-specific code here */ |
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396 | } |
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397 | |
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398 | static void |
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399 | imps_read_config_table(unsigned start, int count) |
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400 | { |
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401 | while (count-- > 0) { |
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402 | switch (*((unsigned char *)start)) { |
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403 | case IMPS_BCT_PROCESSOR: |
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404 | if ( imps_num_cpus < rtems_configuration_smp_maximum_processors ) { |
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405 | add_processor((imps_processor *)start); |
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406 | } else |
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407 | imps_num_cpus++; |
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408 | start += 12; /* 20 total */ |
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409 | break; |
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410 | case IMPS_BCT_BUS: |
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411 | add_bus((imps_bus *)start); |
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412 | break; |
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413 | case IMPS_BCT_IOAPIC: |
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414 | add_ioapic((imps_ioapic *)start); |
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415 | break; |
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416 | #if 0 /* XXXXX uncomment this if "add_io_interrupt" is implemented */ |
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417 | case IMPS_BCT_IO_INTERRUPT: |
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418 | add_io_interrupt((imps_interrupt *)start); |
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419 | break; |
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420 | #endif |
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421 | #if 0 /* XXXXX uncomment this if "add_local_interrupt" is implemented */ |
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422 | case IMPS_BCT_LOCAL_INTERRUPT: |
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423 | add_local_interupt((imps_interrupt *)start); |
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424 | break; |
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425 | #endif |
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426 | default: |
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427 | break; |
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428 | } |
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429 | start += 8; |
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430 | } |
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431 | if ( imps_num_cpus > rtems_configuration_smp_maximum_processors ) { |
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432 | printk( |
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433 | "WARNING!! Found more CPUs (%d) than configured for (%d)!!\n", |
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434 | imps_num_cpus - 1, |
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435 | rtems_configuration_smp_maximum_processors |
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436 | ); |
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437 | imps_num_cpus = rtems_configuration_smp_maximum_processors; |
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438 | return; |
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439 | } |
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440 | } |
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441 | |
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442 | static int |
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443 | imps_bad_bios(imps_fps *fps_ptr) |
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444 | { |
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445 | int sum; |
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446 | imps_cth *local_cth_ptr |
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447 | = (imps_cth *) PHYS_TO_VIRTUAL(fps_ptr->cth_ptr); |
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448 | |
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449 | if (fps_ptr->feature_info[0] > IMPS_FPS_DEFAULT_MAX) { |
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450 | printk(" Invalid MP System Configuration type %d\n", |
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451 | fps_ptr->feature_info[0]); |
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452 | return 1; |
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453 | } |
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454 | |
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455 | if (fps_ptr->cth_ptr) { |
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456 | sum = get_checksum((unsigned)local_cth_ptr, |
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457 | local_cth_ptr->base_length); |
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458 | if (local_cth_ptr->sig != IMPS_CTH_SIGNATURE || sum) { |
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459 | printk( |
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460 | " Bad MP Config Table sig 0x%x and/or checksum 0x%x\n", |
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461 | (unsigned)(fps_ptr->cth_ptr), |
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462 | sum |
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463 | ); |
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464 | return 1; |
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465 | } |
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466 | if (local_cth_ptr->spec_rev != fps_ptr->spec_rev) { |
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467 | printk( |
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468 | " Bad MP Config Table sub-revision # %d\n", |
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469 | local_cth_ptr->spec_rev |
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470 | ); |
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471 | return 1; |
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472 | } |
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473 | if (local_cth_ptr->extended_length) { |
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474 | sum = (get_checksum(((unsigned)local_cth_ptr) |
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475 | + local_cth_ptr->base_length, |
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476 | local_cth_ptr->extended_length) |
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477 | + local_cth_ptr->extended_checksum) & 0xFF; |
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478 | if (sum) { |
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479 | printk(" Bad Extended MP Config Table checksum 0x%x\n", sum); |
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480 | return 1; |
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481 | } |
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482 | } |
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483 | } else if (!fps_ptr->feature_info[0]) { |
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484 | printk(" Missing configuration information\n"); |
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485 | return 1; |
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486 | } |
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487 | |
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488 | return 0; |
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489 | } |
---|
490 | |
---|
491 | static void |
---|
492 | imps_read_bios(imps_fps *fps_ptr) |
---|
493 | { |
---|
494 | int apicid; |
---|
495 | unsigned cth_start, cth_count; |
---|
496 | imps_cth *local_cth_ptr |
---|
497 | = (imps_cth *)PHYS_TO_VIRTUAL(fps_ptr->cth_ptr); |
---|
498 | char *str_ptr; |
---|
499 | |
---|
500 | printk("Intel MultiProcessor Spec 1.%d BIOS support detected\n", |
---|
501 | fps_ptr->spec_rev); |
---|
502 | |
---|
503 | /* |
---|
504 | * Do all checking of errors which would definitely |
---|
505 | * lead to failure of the SMP boot here. |
---|
506 | */ |
---|
507 | if (imps_bad_bios(fps_ptr)) { |
---|
508 | printk(" Disabling MPS support\n"); |
---|
509 | return; |
---|
510 | } |
---|
511 | |
---|
512 | if (fps_ptr->feature_info[1] & IMPS_FPS_IMCRP_BIT) { |
---|
513 | str_ptr = "IMCR and PIC"; |
---|
514 | } else { |
---|
515 | str_ptr = "Virtual Wire"; |
---|
516 | } |
---|
517 | if (fps_ptr->cth_ptr) { |
---|
518 | imps_lapic_addr = local_cth_ptr->lapic_addr; |
---|
519 | } else { |
---|
520 | imps_lapic_addr = LAPIC_ADDR_DEFAULT; |
---|
521 | } |
---|
522 | printk(" APIC config: \"%s mode\" Local APIC address: 0x%x\n", |
---|
523 | str_ptr, imps_lapic_addr); |
---|
524 | if (imps_lapic_addr != (READ_MSR_LO(0x1b) & 0xFFFFF000)) { |
---|
525 | printk("Inconsistent Local APIC address, Disabling SMP support\n"); |
---|
526 | return; |
---|
527 | } |
---|
528 | imps_lapic_addr = PHYS_TO_VIRTUAL(imps_lapic_addr); |
---|
529 | |
---|
530 | /* |
---|
531 | * Setup primary CPU. |
---|
532 | */ |
---|
533 | apicid = IMPS_LAPIC_READ(LAPIC_SPIV); |
---|
534 | IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC); |
---|
535 | apicid = APIC_ID(IMPS_LAPIC_READ(LAPIC_ID)); |
---|
536 | imps_cpu_apic_map[0] = apicid; |
---|
537 | imps_apic_cpu_map[apicid] = 0; |
---|
538 | |
---|
539 | if (fps_ptr->cth_ptr) { |
---|
540 | char str1[16], str2[16]; |
---|
541 | memcpy(str1, local_cth_ptr->oem_id, 8); |
---|
542 | str1[8] = 0; |
---|
543 | memcpy(str2, local_cth_ptr->prod_id, 12); |
---|
544 | str2[12] = 0; |
---|
545 | printk(" OEM id: %s Product id: %s\n", str1, str2); |
---|
546 | cth_start = ((unsigned) local_cth_ptr) + sizeof(imps_cth); |
---|
547 | cth_count = local_cth_ptr->entry_count; |
---|
548 | } else { |
---|
549 | *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) = IOAPIC_ID; |
---|
550 | defconfig.ioapic.id |
---|
551 | = APIC_ID(*((volatile unsigned *) |
---|
552 | (IOAPIC_ADDR_DEFAULT+IOAPIC_RW))); |
---|
553 | *((volatile unsigned *) IOAPIC_ADDR_DEFAULT) = IOAPIC_VER; |
---|
554 | defconfig.ioapic.ver |
---|
555 | = APIC_VERSION(*((volatile unsigned *) |
---|
556 | (IOAPIC_ADDR_DEFAULT+IOAPIC_RW))); |
---|
557 | defconfig.proc[apicid].flags |
---|
558 | = IMPS_FLAG_ENABLED|IMPS_CPUFLAG_BOOT; |
---|
559 | defconfig.proc[!apicid].flags = IMPS_FLAG_ENABLED; |
---|
560 | imps_num_cpus = 2; |
---|
561 | if (fps_ptr->feature_info[0] == 1 |
---|
562 | || fps_ptr->feature_info[0] == 5) { |
---|
563 | memcpy(defconfig.bus[0].bus_type, "ISA ", 6); |
---|
564 | } |
---|
565 | if (fps_ptr->feature_info[0] == 4 |
---|
566 | || fps_ptr->feature_info[0] == 7) { |
---|
567 | memcpy(defconfig.bus[0].bus_type, "MCA ", 6); |
---|
568 | } |
---|
569 | if (fps_ptr->feature_info[0] > 4) { |
---|
570 | defconfig.proc[0].apic_ver = 0x10; |
---|
571 | defconfig.proc[1].apic_ver = 0x10; |
---|
572 | defconfig.bus[1].type = IMPS_BCT_BUS; |
---|
573 | } |
---|
574 | if (fps_ptr->feature_info[0] == 2) { |
---|
575 | defconfig.intin[2].type = 255; |
---|
576 | defconfig.intin[13].type = 255; |
---|
577 | } |
---|
578 | if (fps_ptr->feature_info[0] == 7) { |
---|
579 | defconfig.intin[0].type = 255; |
---|
580 | } |
---|
581 | cth_start = (unsigned) &defconfig; |
---|
582 | cth_count = DEF_ENTRIES; |
---|
583 | } |
---|
584 | imps_read_config_table(cth_start, cth_count); |
---|
585 | |
---|
586 | /* %%%%% ESB read extended entries here */ |
---|
587 | |
---|
588 | imps_enabled = 1; |
---|
589 | } |
---|
590 | |
---|
591 | /* |
---|
592 | * Given a region to check, this actually looks for the "MP Floating |
---|
593 | * Pointer Structure". The return value indicates if the correct |
---|
594 | * signature and checksum for a floating pointer structure of the |
---|
595 | * appropriate spec revision was found. If so, then do not search |
---|
596 | * further. |
---|
597 | * |
---|
598 | * NOTE: The memory scan will always be in the bottom 1 MB. |
---|
599 | * |
---|
600 | * This function presumes that "start" will always be aligned to a 16-bit |
---|
601 | * boundary. |
---|
602 | * |
---|
603 | * Function finished. |
---|
604 | */ |
---|
605 | static int |
---|
606 | imps_scan(unsigned start, unsigned length) |
---|
607 | { |
---|
608 | printk("Scanning from 0x%x for %d bytes\n", start, length); |
---|
609 | |
---|
610 | while (length > 0) { |
---|
611 | imps_fps *fps_ptr = (imps_fps *) PHYS_TO_VIRTUAL(start); |
---|
612 | |
---|
613 | if (fps_ptr->sig == IMPS_FPS_SIGNATURE |
---|
614 | && fps_ptr->length == 1 |
---|
615 | && (fps_ptr->spec_rev == 1 || fps_ptr->spec_rev == 4) |
---|
616 | && !get_checksum(start, 16)) { |
---|
617 | printk("Found MP Floating Structure Pointer at %x\n", start); |
---|
618 | imps_read_bios(fps_ptr); |
---|
619 | return 1; |
---|
620 | } |
---|
621 | |
---|
622 | length -= 16; |
---|
623 | start += 16; |
---|
624 | } |
---|
625 | |
---|
626 | return 0; |
---|
627 | } |
---|
628 | |
---|
629 | #if !defined(__rtems__) |
---|
630 | /* |
---|
631 | * This is the primary function to "force" SMP support, with |
---|
632 | * the assumption that you have consecutively numbered APIC ids. |
---|
633 | */ |
---|
634 | int |
---|
635 | imps_force(int ncpus) |
---|
636 | { |
---|
637 | int apicid, i; |
---|
638 | imps_processor p; |
---|
639 | |
---|
640 | printk("Intel MultiProcessor \"Force\" Support\n"); |
---|
641 | |
---|
642 | imps_lapic_addr = (READ_MSR_LO(0x1b) & 0xFFFFF000); |
---|
643 | imps_lapic_addr = PHYS_TO_VIRTUAL(imps_lapic_addr); |
---|
644 | |
---|
645 | /* |
---|
646 | * Setup primary CPU. |
---|
647 | */ |
---|
648 | apicid = IMPS_LAPIC_READ(LAPIC_SPIV); |
---|
649 | IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC); |
---|
650 | apicid = APIC_ID(IMPS_LAPIC_READ(LAPIC_ID)); |
---|
651 | imps_cpu_apic_map[0] = apicid; |
---|
652 | imps_apic_cpu_map[apicid] = 0; |
---|
653 | |
---|
654 | p.type = 0; |
---|
655 | p.apic_ver = 0x10; |
---|
656 | p.signature = p.features = 0; |
---|
657 | |
---|
658 | for (i = 0; i < ncpus; i++) { |
---|
659 | if (apicid == i) { |
---|
660 | p.flags = IMPS_FLAG_ENABLED | IMPS_CPUFLAG_BOOT; |
---|
661 | } else { |
---|
662 | p.flags = IMPS_FLAG_ENABLED; |
---|
663 | } |
---|
664 | p.apic_id = i; |
---|
665 | add_processor(&p); |
---|
666 | } |
---|
667 | |
---|
668 | return imps_num_cpus; |
---|
669 | } |
---|
670 | #endif |
---|
671 | |
---|
672 | /* |
---|
673 | * This is the primary function for probing for MPS compatible hardware |
---|
674 | * and BIOS information. Call this during the early stages of OS startup, |
---|
675 | * before memory can be messed up. |
---|
676 | * |
---|
677 | * The probe looks for the "MP Floating Pointer Structure" at locations |
---|
678 | * listed at the top of page 4-2 of the spec. |
---|
679 | * |
---|
680 | * Environment requirements from the OS to run: |
---|
681 | * |
---|
682 | * (1) : A non-linear virtual to physical memory mapping is probably OK, |
---|
683 | * as (I think) the structures all fall within page boundaries, |
---|
684 | * but a linear mapping is recommended. Currently assumes that |
---|
685 | * the mapping will remain identical over time (which should be |
---|
686 | * OK since it only accesses memory which shouldn't be munged |
---|
687 | * by the OS anyway). |
---|
688 | * (2) : The OS only consumes memory which the BIOS says is OK to use, |
---|
689 | * and not any of the BIOS standard areas (the areas 0x400 to |
---|
690 | * 0x600, the EBDA, 0xE0000 to 0xFFFFF, and unreported physical |
---|
691 | * RAM). Sometimes a small amount of physical RAM is not |
---|
692 | * reported by the BIOS, to be used to store MPS and other |
---|
693 | * information. |
---|
694 | * (3) : It must be possible to read the CMOS. |
---|
695 | * (4) : There must be between 512K and 640K of lower memory (this is a |
---|
696 | * sanity check). |
---|
697 | * |
---|
698 | * Function finished. |
---|
699 | */ |
---|
700 | int |
---|
701 | imps_probe(void) |
---|
702 | { |
---|
703 | /* |
---|
704 | * Determine possible address of the EBDA |
---|
705 | */ |
---|
706 | unsigned ebda_addr = *((unsigned short *) |
---|
707 | PHYS_TO_VIRTUAL(EBDA_SEG_ADDR)) << 4; |
---|
708 | |
---|
709 | /* |
---|
710 | * Determine amount of installed lower memory (not *available* |
---|
711 | * lower memory). |
---|
712 | * |
---|
713 | * NOTE: This should work reliably as long as we verify the |
---|
714 | * machine is at least a system that could possibly have |
---|
715 | * MPS compatibility to begin with. |
---|
716 | */ |
---|
717 | unsigned mem_lower = ((CMOS_READ_BYTE(CMOS_BASE_MEMORY+1) << 8) |
---|
718 | | CMOS_READ_BYTE(CMOS_BASE_MEMORY)) << 10; |
---|
719 | |
---|
720 | #ifdef IMPS_DEBUG |
---|
721 | imps_enabled = 0; |
---|
722 | imps_num_cpus = 1; |
---|
723 | #endif |
---|
724 | |
---|
725 | /* |
---|
726 | * Sanity check : if this isn't reasonable, it is almost impossibly |
---|
727 | * unlikely to be an MPS compatible machine, so return failure. |
---|
728 | */ |
---|
729 | if (mem_lower < 512*1024 || mem_lower > 640*1024) { |
---|
730 | return 0; |
---|
731 | } |
---|
732 | |
---|
733 | if (ebda_addr > mem_lower - 1024 |
---|
734 | || ebda_addr + *((unsigned char *) PHYS_TO_VIRTUAL(ebda_addr)) |
---|
735 | * 1024 > mem_lower) { |
---|
736 | ebda_addr = 0; |
---|
737 | } |
---|
738 | |
---|
739 | if (((ebda_addr && imps_scan(ebda_addr, 1024)) |
---|
740 | || (!ebda_addr && imps_scan(mem_lower - 1024, 1024)) |
---|
741 | || imps_scan(0xF0000, 0x10000)) && imps_enabled) { |
---|
742 | return imps_num_cpus; |
---|
743 | } |
---|
744 | |
---|
745 | /* |
---|
746 | * If no BIOS info on MPS hardware is found, then return failure. |
---|
747 | */ |
---|
748 | |
---|
749 | return 0; |
---|
750 | } |
---|
751 | |
---|
752 | /* |
---|
753 | * RTEMS SMP BSP Support |
---|
754 | */ |
---|
755 | void smp_apic_ack(void) |
---|
756 | { |
---|
757 | (void) IMPS_LAPIC_READ(LAPIC_SPIV); /* dummy read */ |
---|
758 | IMPS_LAPIC_WRITE(LAPIC_EOI, 0 ); /* ACK the interrupt */ |
---|
759 | } |
---|
760 | |
---|
761 | rtems_isr ap_ipi_isr( |
---|
762 | rtems_vector_number vector |
---|
763 | ) |
---|
764 | { |
---|
765 | smp_apic_ack(); |
---|
766 | |
---|
767 | rtems_smp_process_interrupt(); |
---|
768 | } |
---|
769 | |
---|
770 | #include <rtems/irq.h> |
---|
771 | |
---|
772 | static rtems_irq_connect_data apIPIIrqData = { |
---|
773 | 16, |
---|
774 | (void *)ap_ipi_isr, |
---|
775 | 0, |
---|
776 | NULL, /* On */ |
---|
777 | NULL, /* Off */ |
---|
778 | NULL, /* IsOn */ |
---|
779 | }; |
---|
780 | |
---|
781 | extern void bsp_reset(void); |
---|
782 | void ipi_install_irq(void) |
---|
783 | { |
---|
784 | if (!BSP_install_rtems_irq_handler (&apIPIIrqData)) { |
---|
785 | printk("Unable to initialize IPI\n"); |
---|
786 | bsp_reset(); |
---|
787 | } |
---|
788 | } |
---|
789 | |
---|
790 | #ifdef __SSE__ |
---|
791 | extern void enable_sse(void); |
---|
792 | #endif |
---|
793 | |
---|
794 | /* pc386 specific initialization */ |
---|
795 | void bsp_smp_secondary_cpu_initialize(int cpu) |
---|
796 | { |
---|
797 | int apicid; |
---|
798 | |
---|
799 | asm volatile( "lidt IDT_Descriptor" ); |
---|
800 | |
---|
801 | apicid = IMPS_LAPIC_READ(LAPIC_SPIV); |
---|
802 | IMPS_LAPIC_WRITE(LAPIC_SPIV, apicid|LAPIC_SPIV_ENABLE_APIC); |
---|
803 | |
---|
804 | #ifdef __SSE__ |
---|
805 | enable_sse(); |
---|
806 | #endif |
---|
807 | } |
---|
808 | |
---|
809 | #include <rtems/bspsmp.h> |
---|
810 | int bsp_smp_initialize( |
---|
811 | int maximum |
---|
812 | ) |
---|
813 | { |
---|
814 | int cores; |
---|
815 | /* XXX need to deal with finding too many cores */ |
---|
816 | |
---|
817 | cores = imps_probe(); |
---|
818 | |
---|
819 | if ( cores > 1 ) |
---|
820 | ipi_install_irq(); |
---|
821 | return cores; |
---|
822 | } |
---|
823 | |
---|
824 | void bsp_smp_interrupt_cpu( |
---|
825 | int cpu |
---|
826 | ) |
---|
827 | { |
---|
828 | send_ipi( cpu, 0x30 ); |
---|
829 | } |
---|
830 | |
---|
831 | void bsp_smp_broadcast_interrupt(void) |
---|
832 | { |
---|
833 | /* Single broadcast interrupt */ |
---|
834 | send_ipi( 0, LAPIC_ICR_DS_ALLEX | 0x30 ); |
---|
835 | } |
---|
836 | |
---|
837 | void bsp_smp_wait_for( |
---|
838 | volatile unsigned int *address, |
---|
839 | unsigned int desired, |
---|
840 | int maximum_usecs |
---|
841 | ) |
---|
842 | { |
---|
843 | int iterations; |
---|
844 | volatile int i; |
---|
845 | volatile unsigned int *p = (volatile unsigned int *)address; |
---|
846 | |
---|
847 | for (iterations=0 ; iterations < maximum_usecs ; iterations++ ) { |
---|
848 | if ( *p == desired ) |
---|
849 | break; |
---|
850 | #ifdef __SSE3__ |
---|
851 | __builtin_ia32_monitor( (const void *)address, 0, 0 ); |
---|
852 | if ( *p == desired ) |
---|
853 | break; |
---|
854 | __builtin_ia32_mwait( 0, 0 ); |
---|
855 | #endif |
---|
856 | |
---|
857 | /* |
---|
858 | * Until i386 ms delay does not depend upon the clock we |
---|
859 | * will use this less sophisticated delay. |
---|
860 | */ |
---|
861 | for(i=5000; i>0; i--) |
---|
862 | ; |
---|
863 | } |
---|
864 | } |
---|