1 | /* irq.c |
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2 | * |
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3 | * This file contains the implementation of the function described in irq.h |
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4 | * |
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5 | * CopyRight (C) 1998 valette@crf.canon.fr |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in found in the file LICENSE in this distribution or at |
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9 | * http://www.OARcorp.com/rtems/license.html. |
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10 | * |
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11 | * $Id$ |
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12 | */ |
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13 | |
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14 | #include "asm.h" |
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15 | #include <irq_asm.h> |
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16 | |
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17 | .set SAVED_REGS , 32 # space consumed by saved regs |
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18 | .set EIP_OFFSET , SAVED_REGS # offset of tasks eip |
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19 | .set CS_OFFSET , EIP_OFFSET+4 # offset of tasks code segment |
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20 | .set EFLAGS_OFFSET , CS_OFFSET+4 # offset of tasks eflags |
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21 | |
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22 | |
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23 | /*PAGE |
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24 | * void _New_ISR_Displatch() |
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25 | * |
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26 | * Entry point from the outermost interrupt service routine exit. |
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27 | * The current stack is the supervisor mode stack. |
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28 | */ |
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29 | |
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30 | PUBLIC (_New_ISR_Displatch) |
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31 | SYM (_New_ISR_Displatch): |
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32 | |
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33 | call SYM (_Thread_Dispatch) # invoke Dispatcher |
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34 | |
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35 | /* |
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36 | * BEGINNING OF DE-ESTABLISH SEGMENTS |
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37 | * |
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38 | * NOTE: Make sure there is code here if code is added to |
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39 | * load the segment registers. |
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40 | * |
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41 | */ |
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42 | |
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43 | /***** DE-ESTABLISH SEGMENTS CODE GOES HERE ****/ |
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44 | |
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45 | /* |
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46 | * END OF DE-ESTABLISH SEGMENTS |
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47 | */ |
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48 | |
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49 | popa # restore general registers |
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50 | iret # return to interrupted thread |
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51 | |
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52 | |
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53 | SYM (_New_ISR_Handler): |
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54 | /* |
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55 | * Before this was point is reached the vectors unique |
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56 | * entry point did the following: |
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57 | * |
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58 | * 1. saved sctach registers registers eax edx ecx" |
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59 | * 2. put the vector number in ecx. |
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60 | * |
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61 | * BEGINNING OF ESTABLISH SEGMENTS |
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62 | * |
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63 | * WARNING: If an interrupt can occur when the segments are |
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64 | * not correct, then this is where we should establish |
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65 | * the segments. In addition to establishing the |
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66 | * segments, it may be necessary to establish a stack |
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67 | * in the current data area on the outermost interrupt. |
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68 | * |
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69 | * NOTE: If the previous values of the segment registers are |
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70 | * pushed, do not forget to adjust SAVED_REGS. |
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71 | * |
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72 | * NOTE: Make sure the exit code which restores these |
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73 | * when this type of code is needed. |
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74 | */ |
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75 | |
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76 | /***** ESTABLISH SEGMENTS CODE GOES HERE ******/ |
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77 | |
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78 | /* |
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79 | * END OF ESTABLISH SEGMENTS |
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80 | */ |
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81 | |
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82 | /* |
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83 | * Now switch stacks if necessary |
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84 | */ |
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85 | |
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86 | movw SYM (i8259s_cache), ax # move current i8259 interrupt mask in ax |
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87 | pushl eax # push it on the stack |
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88 | /* |
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89 | * compute the new PIC mask: |
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90 | * |
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91 | * <new mask> = <old mask> | irq_mask_or_tbl[<intr number aka ecx>] |
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92 | */ |
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93 | movw SYM (irq_mask_or_tbl) (,ecx,2), dx |
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94 | orw dx, ax |
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95 | /* |
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96 | * Install new computed value on the i8259 and update cache |
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97 | * accordingly |
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98 | */ |
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99 | movw ax, SYM (i8259s_cache) |
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100 | outb $PIC_MASTER_IMR_IO_PORT |
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101 | movb ah, al |
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102 | outb $PIC_SLAVE_IMR_IO_PORT |
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103 | |
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104 | /* |
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105 | * acknowledge the interrupt |
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106 | * |
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107 | */ |
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108 | movb $PIC_EOI, al |
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109 | cmpl $7, ecx |
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110 | jbe .master |
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111 | outb $PIC_SLAVE_COMMAND_IO_PORT |
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112 | .master: |
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113 | outb $PIC_MASTER_COMMAND_IO_PORT |
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114 | |
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115 | .check_stack_switch: |
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116 | pushl ebp |
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117 | movl esp, ebp # ebp = previous stack pointer |
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118 | cmpl $0, SYM (_ISR_Nest_level) # is this the outermost interrupt? |
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119 | jne nested # No, then continue |
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120 | movl SYM (_CPU_Interrupt_stack_high), esp |
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121 | |
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122 | /* |
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123 | * We want to insure that the old stack pointer is on the |
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124 | * stack we will be on at the end of the ISR when we restore it. |
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125 | * By saving it on every interrupt, all we have to do is pop it |
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126 | * near the end of every interrupt. |
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127 | */ |
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128 | |
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129 | nested: |
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130 | incl SYM (_ISR_Nest_level) # one nest level deeper |
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131 | incl SYM (_Thread_Dispatch_disable_level) # disable multitasking |
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132 | /* |
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133 | * re-enable interrupts at processor level as the current |
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134 | * interrupt source is now masked via i8259 |
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135 | */ |
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136 | sti |
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137 | |
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138 | /* |
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139 | * ECX is preloaded with the vector number but it is a scratch register |
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140 | * so we must save it again. |
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141 | */ |
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142 | |
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143 | pushl ecx # push vector number |
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144 | mov SYM (current_irq) (,ecx,4),eax |
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145 | # eax = Users handler |
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146 | call *eax # invoke user ISR |
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147 | /* |
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148 | * disable interrupts_again |
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149 | */ |
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150 | cli |
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151 | popl ecx # ecx = vector number |
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152 | /* |
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153 | * restore stack |
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154 | */ |
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155 | movl ebp, esp |
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156 | popl ebp |
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157 | |
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158 | /* |
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159 | * restore the original i8259 masks |
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160 | */ |
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161 | popl eax |
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162 | movw ax, SYM (i8259s_cache) |
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163 | outb $PIC_MASTER_IMR_IO_PORT |
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164 | movb ah, al |
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165 | outb $PIC_SLAVE_IMR_IO_PORT |
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166 | |
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167 | |
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168 | decl SYM (_ISR_Nest_level) # one less ISR nest level |
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169 | # If interrupts are nested, |
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170 | # then dispatching is disabled |
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171 | |
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172 | decl SYM (_Thread_Dispatch_disable_level) |
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173 | # unnest multitasking |
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174 | # Is dispatch disabled |
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175 | jne .exit # Yes, then exit |
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176 | |
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177 | cmpl $0, SYM (_Context_Switch_necessary) |
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178 | # Is task switch necessary? |
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179 | jne bframe # Yes, then build stack |
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180 | |
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181 | cmpl $0, SYM (_ISR_Signals_to_thread_executing) |
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182 | # signals sent to Run_thread |
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183 | # while in interrupt handler? |
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184 | je .exit # No, exit |
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185 | |
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186 | bframe: |
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187 | movl $0, SYM (_ISR_Signals_to_thread_executing) |
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188 | /* |
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189 | * complete code as if a pusha had been executed on entry |
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190 | */ |
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191 | pushl ebx |
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192 | pushl esp |
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193 | pushl ebp |
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194 | pushl esi |
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195 | pushl edi |
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196 | # push the isf for Isr_dispatch |
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197 | pushl EFLAGS_OFFSET(esp) # push tasks eflags |
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198 | push cs # cs of Isr_dispatch |
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199 | pushl $ SYM (_New_ISR_Displatch)# entry point |
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200 | iret |
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201 | |
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202 | .exit: |
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203 | /* |
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204 | * BEGINNING OF DE-ESTABLISH SEGMENTS |
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205 | * |
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206 | * NOTE: Make sure there is code here if code is added to |
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207 | * load the segment registers. |
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208 | * |
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209 | */ |
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210 | |
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211 | /******* DE-ESTABLISH SEGMENTS CODE GOES HERE ********/ |
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212 | |
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213 | /* |
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214 | * END OF DE-ESTABLISH SEGMENTS |
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215 | */ |
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216 | popl edx |
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217 | popl ecx |
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218 | popl eax |
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219 | iret |
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220 | |
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221 | #define DISTINCT_INTERRUPT_ENTRY(_vector) \ |
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222 | .p2align 4 ; \ |
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223 | PUBLIC (rtems_irq_prologue_ ## _vector ) ; \ |
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224 | SYM (rtems_irq_prologue_ ## _vector ): \ |
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225 | pushl eax ; \ |
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226 | pushl ecx ; \ |
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227 | pushl edx ; \ |
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228 | movl $ _vector, ecx ; \ |
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229 | jmp SYM (_New_ISR_Handler) ; |
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230 | |
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231 | DISTINCT_INTERRUPT_ENTRY(0) |
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232 | DISTINCT_INTERRUPT_ENTRY(1) |
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233 | DISTINCT_INTERRUPT_ENTRY(2) |
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234 | DISTINCT_INTERRUPT_ENTRY(3) |
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235 | DISTINCT_INTERRUPT_ENTRY(4) |
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236 | DISTINCT_INTERRUPT_ENTRY(5) |
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237 | DISTINCT_INTERRUPT_ENTRY(6) |
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238 | DISTINCT_INTERRUPT_ENTRY(7) |
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239 | DISTINCT_INTERRUPT_ENTRY(8) |
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240 | DISTINCT_INTERRUPT_ENTRY(9) |
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241 | DISTINCT_INTERRUPT_ENTRY(10) |
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242 | DISTINCT_INTERRUPT_ENTRY(11) |
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243 | DISTINCT_INTERRUPT_ENTRY(12) |
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244 | DISTINCT_INTERRUPT_ENTRY(13) |
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245 | DISTINCT_INTERRUPT_ENTRY(14) |
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246 | DISTINCT_INTERRUPT_ENTRY(15) |
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247 | |
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248 | /* |
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249 | * routine used to initialize the IDT by default |
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250 | */ |
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251 | |
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252 | PUBLIC (default_raw_idt_handler) |
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253 | PUBLIC (raw_idt_notify) |
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254 | |
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255 | SYM (default_raw_idt_handler): |
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256 | pusha |
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257 | cld |
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258 | call raw_idt_notify |
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259 | popa |
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260 | iret |
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261 | |
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