1 | /** |
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2 | * @file |
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3 | * @ingroup i386_irq |
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4 | * @brief |
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5 | */ |
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6 | |
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7 | /* irq_asm.h |
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8 | * |
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9 | * This include file has defines to represent some contant used |
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10 | * to program and manage the Intel 8259 interrupt controller |
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11 | * |
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12 | * |
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13 | * COPYRIGHT (c) 1998 valette@crf.canon.fr |
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14 | * |
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15 | * Copyright (c) 2016 Chris Johns <chrisj@rtems.org> |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.org/license/LICENSE. |
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20 | */ |
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21 | #ifndef __I8259S_H__ |
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22 | #define __I8259S_H__ |
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23 | |
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24 | #define BSP_ASM_IRQ_VECTOR_BASE 0x20 |
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25 | /** @brief PIC's command and mask registers */ |
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26 | #define PIC_MASTER_COMMAND_IO_PORT 0x20 ///< Master PIC command register |
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27 | #define PIC_SLAVE_COMMAND_IO_PORT 0xa0 ///< Slave PIC command register |
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28 | #define PIC_MASTER_IMR_IO_PORT 0x21 ///< Master PIC Interrupt Mask Register |
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29 | #define PIC_SLAVE_IMR_IO_PORT 0xa1 ///< Slave PIC Interrupt Mask Register |
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30 | |
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31 | /** @brief Command for specific EOI (End Of Interrupt): Interrupt acknowledge */ |
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32 | #define PIC_EOSI 0x60 ///< End of Specific Interrupt (EOSI) |
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33 | #define PIC_EOI 0x20 ///< Generic End of Interrupt (EOI) |
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34 | |
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35 | /* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */ |
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36 | #define PIC_OCW3_RIS 0x01 /* 1 = read IS, 0 = read IR */ |
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37 | #define PIC_OCW3_RR 0x02 /* register read */ |
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38 | #define PIC_OCW3_P 0x04 /* poll mode command */ |
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39 | /* 0x08 must be 1 to select OCW3 vs OCW2 */ |
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40 | #define PIC_OCW3_SEL 0x08 /* must be 1 */ |
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41 | /* 0x10 must be 0 to select OCW3 vs ICW1 */ |
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42 | #define PIC_OCW3_SMM 0x20 /* special mode mask */ |
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43 | #define PIC_OCW3_ESMM 0x40 /* enable SMM */ |
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44 | |
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45 | #endif |
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