source: rtems/c/src/lib/libbsp/i386/shared/irq/irq_asm.h @ 55b3616

4.104.114.84.95
Last change on this file since 55b3616 was 0ebbf66, checked in by Joel Sherrill <joel.sherrill@…>, on 10/05/98 at 22:36:06

Large patch from Erik Ivanenko <erik.ivanenko@…> which
moves pieces of the pc386 bsp up to a shared level for all i386 BSPs
and modifies the i386ex BSP to use those shared pieces. Serial remote
debugging is included for both targets. Erik's notes:

There are several workarounds in it:

1) #define NEXT_GAS is hardcoded in pc386/start/start.s
2) #define NEXT_GAS is hardcoded in i386ex/start/start.s
3) #define NEW_GAS is hardcoded in pc386/start16.s
4) #undef assert and redeclare _assert hardcoded in console.c for

both pc386 and i386ex due to my egcs1.1b ~ newlib problem. Should have
modified t-rtems.cfg ( no time )

I've tested pc386 with both video and serial consoles and GDB remote.
All work fine, except that GDB acts weird. ( re: other posting)

I hope this will work for you. It took quite some time to locate the
autoconf error. The remainder was just grunt work.
Unfortunately, I think I've unwound the removal of the IBMPCInitVideo
stuff. Sorry. I REALLY can't spend more time... I've been at this
conversion to 4.0 locally and updating the release since Sept. 8th, and
have yet to compile my network driver.... This is as much as I can do
right now.

I look forward to the next patch to really test i368ex. I did make sure
that the sample tests worked for pc386.
  • Property mode set to 100644
File size: 1023 bytes
Line 
1/* irq_asm.h
2 *
3 *  This include file has defines to represent some contant used
4 *  to program and manage the  Intel 8259 interrupt controller
5 *
6 *
7 *  COPYRIGHT (c) 1998 valette@crf.canon.fr
8 *
9 *  The license and distribution terms for this file may be
10 *  found in found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15#ifndef __IRQ_ASM_H__
16#define __IRQ_ASM_H__
17
18#define BSP_ASM_IRQ_VECTOR_BASE 0x20
19    /* PIC's command and mask registers */
20#define PIC_MASTER_COMMAND_IO_PORT              0x20    /* Master PIC command register */
21#define PIC_SLAVE_COMMAND_IO_PORT               0xa0    /* Slave PIC command register */
22#define PIC_MASTER_IMR_IO_PORT                  0x21    /* Master PIC Interrupt Mask Register */
23#define PIC_SLAVE_IMR_IO_PORT                   0xa1    /* Slave PIC Interrupt Mask Register */
24
25    /* Command for specific EOI (End Of Interrupt): Interrupt acknowledge */
26#define PIC_EOSI        0x60    /* End of Specific Interrupt (EOSI) */
27#define PIC_EOI         0x20    /* Generic End of Interrupt (EOI) */
28
29
30#endif
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