[1ecb21d8] | 1 | /* |
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[67a2288] | 2 | * This file contains the implementation of the function described in irq.h |
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[1ecb21d8] | 3 | */ |
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| 4 | |
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| 5 | /* |
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[591b760] | 6 | * Copyright (C) 1998 valette@crf.canon.fr |
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[67a2288] | 7 | * |
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[66729db3] | 8 | * COPYRIGHT (c) 1989-2011. |
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| 9 | * On-Line Applications Research Corporation (OAR). |
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| 10 | * |
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[67a2288] | 11 | * The license and distribution terms for this file may be |
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[b8fc2de1] | 12 | * found in found in the file LICENSE in this distribution or at |
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[c499856] | 13 | * http://www.rtems.org/license/LICENSE. |
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[67a2288] | 14 | */ |
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| 15 | |
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[a1e601d] | 16 | #include <rtems/asm.h> |
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[66729db3] | 17 | #include <rtems/system.h> |
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[15519cb] | 18 | #include <bspopts.h> |
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[abf41fd] | 19 | #include <rtems/score/cpu.h> |
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[15519cb] | 20 | #include <rtems/score/percpu.h> |
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[abf41fd] | 21 | |
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[1ecb21d8] | 22 | #include <bsp.h> /* to establish dependency on prototype */ |
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| 23 | |
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[abf41fd] | 24 | #ifndef CPU_STACK_ALIGNMENT |
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| 25 | #error "Missing header? CPU_STACK_ALIGNMENT is not defined here" |
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| 26 | #endif |
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[67a2288] | 27 | |
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[385212f] | 28 | /* Stack frame we use for intermediate storage */ |
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| 29 | #define ARG_OFF 0 |
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[93fb8797] | 30 | #define MSK_OFF 4 /* not used any more */ |
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[15519cb] | 31 | #define EBX_OFF 8 /* ebx */ |
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| 32 | #define EBP_OFF 12 /* code restoring ebp/esp relies on */ |
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| 33 | #define ESP_OFF 16 /* esp being on top of ebp! */ |
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[4a4201c] | 34 | #ifdef __SSE__ |
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[01f2692e] | 35 | /* need to be on 16 byte boundary for SSE, add 12 to do that */ |
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[3bc1585c] | 36 | #define FRM_SIZ (20+12+512) |
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| 37 | #define SSE_OFF 32 |
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[4a4201c] | 38 | #else |
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[15519cb] | 39 | #define FRM_SIZ 20 |
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[4a4201c] | 40 | #endif |
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[385212f] | 41 | |
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[287e4a8b] | 42 | BEGIN_CODE |
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[6128a4a] | 43 | |
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| 44 | SYM (_ISR_Handler): |
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[287e4a8b] | 45 | /* |
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| 46 | * Before this was point is reached the vectors unique |
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| 47 | * entry point did the following: |
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| 48 | * |
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[55b1aee4] | 49 | * 1. saved scratch registers registers eax edx ecx" |
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[287e4a8b] | 50 | * 2. put the vector number in ecx. |
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| 51 | * |
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[55b1aee4] | 52 | * BEGINNING OF ESTABLISH SEGMENTS |
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| 53 | * |
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| 54 | * WARNING: If an interrupt can occur when the segments are |
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| 55 | * not correct, then this is where we should establish |
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| 56 | * the segments. In addition to establishing the |
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| 57 | * segments, it may be necessary to establish a stack |
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| 58 | * in the current data area on the outermost interrupt. |
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| 59 | * |
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[287e4a8b] | 60 | * NOTE: If the previous values of the segment registers are |
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| 61 | * pushed, do not forget to adjust SAVED_REGS. |
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| 62 | * |
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| 63 | * NOTE: Make sure the exit code which restores these |
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| 64 | * when this type of code is needed. |
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| 65 | */ |
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| 66 | |
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| 67 | /***** ESTABLISH SEGMENTS CODE GOES HERE ******/ |
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| 68 | |
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| 69 | /* |
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| 70 | * END OF ESTABLISH SEGMENTS |
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| 71 | */ |
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| 72 | |
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| 73 | /* |
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[385212f] | 74 | * Establish an aligned stack frame |
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[15519cb] | 75 | * original sp |
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| 76 | * saved ebx |
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| 77 | * saved ebp |
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| 78 | * saved irq mask |
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[93fb8797] | 79 | * vector arg to BSP_dispatch_isr <- aligned SP |
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[287e4a8b] | 80 | */ |
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[385212f] | 81 | movl esp, eax |
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| 82 | subl $FRM_SIZ, esp |
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| 83 | andl $ - CPU_STACK_ALIGNMENT, esp |
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[15519cb] | 84 | movl ebx, EBX_OFF(esp) |
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[385212f] | 85 | movl eax, ESP_OFF(esp) |
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| 86 | movl ebp, EBP_OFF(esp) |
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[287e4a8b] | 87 | |
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[93fb8797] | 88 | /* |
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| 89 | * GCC versions starting with 4.3 no longer place the cld |
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| 90 | * instruction before string operations. We need to ensure |
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| 91 | * it is set correctly for ISR handlers. |
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| 92 | */ |
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| 93 | cld |
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| 94 | |
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[4a4201c] | 95 | #ifdef __SSE__ |
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| 96 | /* NOTE: SSE only is supported if the BSP enables fxsave/fxrstor |
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| 97 | * to save/restore SSE context! This is so far only implemented |
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| 98 | * for pc386!. |
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| 99 | */ |
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| 100 | |
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| 101 | /* We save SSE here (on the task stack) because we possibly |
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[15519cb] | 102 | * call other C-code (besides the ISR, namely _Thread_Dispatch()) |
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[4a4201c] | 103 | */ |
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| 104 | /* don't wait here; a possible exception condition will eventually be |
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| 105 | * detected when the task resumes control and executes a FP instruction |
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| 106 | fwait |
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| 107 | */ |
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| 108 | fxsave SSE_OFF(esp) |
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| 109 | fninit /* clean-slate FPU */ |
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| 110 | movl $0x1f80, ARG_OFF(esp) /* use ARG_OFF as scratch space */ |
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| 111 | ldmxcsr ARG_OFF(esp) /* clean-slate MXCSR */ |
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| 112 | #endif |
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| 113 | |
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[55b1aee4] | 114 | /* |
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| 115 | * Now switch stacks if necessary |
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| 116 | */ |
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| 117 | |
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| 118 | PUBLIC (ISR_STOP) |
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| 119 | ISR_STOP: |
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| 120 | .check_stack_switch: |
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| 121 | movl esp, ebp /* ebp = previous stack pointer */ |
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| 122 | |
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[4e3b7e26] | 123 | #ifdef RTEMS_SMP |
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| 124 | call SYM(_CPU_SMP_Get_current_processor) |
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| 125 | sall $PER_CPU_CONTROL_SIZE_LOG2, eax |
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| 126 | addl $SYM(_Per_CPU_Information), eax |
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| 127 | movl eax, ebx |
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| 128 | #else |
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[55b1aee4] | 129 | movl $SYM(_Per_CPU_Information), ebx |
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[4e3b7e26] | 130 | #endif |
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[55b1aee4] | 131 | |
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| 132 | /* is this the outermost interrupt? */ |
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| 133 | cmpl $0, PER_CPU_ISR_NEST_LEVEL(ebx) |
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| 134 | jne nested /* No, then continue */ |
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| 135 | movl PER_CPU_INTERRUPT_STACK_HIGH(ebx), esp |
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| 136 | |
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| 137 | /* |
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| 138 | * We want to insure that the old stack pointer is in ebp |
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| 139 | * By saving it on every interrupt, all we have to do is |
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| 140 | * movl ebp->esp near the end of every interrupt. |
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| 141 | */ |
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| 142 | |
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| 143 | nested: |
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| 144 | incl PER_CPU_ISR_NEST_LEVEL(ebx) /* one nest level deeper */ |
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[4e3b7e26] | 145 | incl PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx) /* disable |
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| 146 | multitasking */ |
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[15519cb] | 147 | /* |
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[385212f] | 148 | * ECX is preloaded with the vector number; store as arg |
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| 149 | * on top of stack. Note that _CPU_Interrupt_stack_high |
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| 150 | * was adjusted in _CPU_Interrupt_stack_setup() (score/rtems/cpu.h) |
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| 151 | * to make sure there is space. |
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[67a2288] | 152 | */ |
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[6128a4a] | 153 | |
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[385212f] | 154 | movl ecx, ARG_OFF(esp) /* store vector arg in stack */ |
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[93fb8797] | 155 | call BSP_dispatch_isr |
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[abf41fd] | 156 | |
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[15519cb] | 157 | movl ARG_OFF(esp), ecx /* grab vector arg from stack */ |
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| 158 | |
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[67a2288] | 159 | /* |
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[385212f] | 160 | * Restore stack. This moves back to the task stack |
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| 161 | * when all interrupts are unnested. |
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[67a2288] | 162 | */ |
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[287e4a8b] | 163 | movl ebp, esp |
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[67a2288] | 164 | |
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[15519cb] | 165 | decl PER_CPU_ISR_NEST_LEVEL(ebx) /* one less ISR nest level */ |
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[287e4a8b] | 166 | /* If interrupts are nested, */ |
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| 167 | /* then dispatching is disabled */ |
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[67a2288] | 168 | |
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[4e3b7e26] | 169 | decl PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(ebx) |
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[287e4a8b] | 170 | /* unnest multitasking */ |
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| 171 | /* Is dispatch disabled */ |
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| 172 | jne .exit /* Yes, then exit */ |
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[67a2288] | 173 | |
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[15519cb] | 174 | cmpb $0, PER_CPU_DISPATCH_NEEDED(ebx) |
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[287e4a8b] | 175 | /* Is task switch necessary? */ |
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| 176 | jne .schedule /* Yes, then call the scheduler */ |
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[15519cb] | 177 | jmp .exit /* No, exit */ |
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[6128a4a] | 178 | |
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[8b2ee37c] | 179 | .schedule: |
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| 180 | /* |
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| 181 | * the scratch registers have already been saved and we are already |
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[5fbf42c] | 182 | * back on the thread system stack. So we can call _Thread_Dispatch |
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[8b2ee37c] | 183 | * directly |
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| 184 | */ |
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[287e4a8b] | 185 | call _Thread_Dispatch |
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[8b2ee37c] | 186 | /* |
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| 187 | * fall through exit to restore complete contex (scratch registers |
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| 188 | * eip, CS, Flags). |
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| 189 | */ |
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[67a2288] | 190 | .exit: |
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[4a4201c] | 191 | |
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| 192 | #ifdef __SSE__ |
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| 193 | fwait |
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| 194 | fxrstor SSE_OFF(esp) |
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| 195 | #endif |
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| 196 | |
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[15519cb] | 197 | /* restore ebx, ebp and original esp */ |
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| 198 | addl $EBX_OFF, esp |
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| 199 | popl ebx |
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[385212f] | 200 | popl ebp |
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| 201 | popl esp |
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[15519cb] | 202 | |
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[287e4a8b] | 203 | /* |
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| 204 | * BEGINNING OF DE-ESTABLISH SEGMENTS |
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| 205 | * |
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| 206 | * NOTE: Make sure there is code here if code is added to |
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| 207 | * load the segment registers. |
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| 208 | * |
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| 209 | */ |
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| 210 | |
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| 211 | /******* DE-ESTABLISH SEGMENTS CODE GOES HERE ********/ |
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| 212 | |
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| 213 | /* |
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| 214 | * END OF DE-ESTABLISH SEGMENTS |
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| 215 | */ |
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| 216 | popl edx |
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| 217 | popl ecx |
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| 218 | popl eax |
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[67a2288] | 219 | iret |
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[8b2ee37c] | 220 | |
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[67a2288] | 221 | #define DISTINCT_INTERRUPT_ENTRY(_vector) \ |
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[287e4a8b] | 222 | .p2align 4 ; \ |
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| 223 | PUBLIC (rtems_irq_prologue_ ## _vector ) ; \ |
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[67a2288] | 224 | SYM (rtems_irq_prologue_ ## _vector ): \ |
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[287e4a8b] | 225 | pushl eax ; \ |
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| 226 | pushl ecx ; \ |
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| 227 | pushl edx ; \ |
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| 228 | movl $ _vector, ecx ; \ |
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| 229 | jmp SYM (_ISR_Handler) ; |
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[67a2288] | 230 | |
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| 231 | DISTINCT_INTERRUPT_ENTRY(0) |
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| 232 | DISTINCT_INTERRUPT_ENTRY(1) |
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| 233 | DISTINCT_INTERRUPT_ENTRY(2) |
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| 234 | DISTINCT_INTERRUPT_ENTRY(3) |
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| 235 | DISTINCT_INTERRUPT_ENTRY(4) |
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| 236 | DISTINCT_INTERRUPT_ENTRY(5) |
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| 237 | DISTINCT_INTERRUPT_ENTRY(6) |
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| 238 | DISTINCT_INTERRUPT_ENTRY(7) |
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| 239 | DISTINCT_INTERRUPT_ENTRY(8) |
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| 240 | DISTINCT_INTERRUPT_ENTRY(9) |
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| 241 | DISTINCT_INTERRUPT_ENTRY(10) |
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| 242 | DISTINCT_INTERRUPT_ENTRY(11) |
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| 243 | DISTINCT_INTERRUPT_ENTRY(12) |
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| 244 | DISTINCT_INTERRUPT_ENTRY(13) |
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| 245 | DISTINCT_INTERRUPT_ENTRY(14) |
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| 246 | DISTINCT_INTERRUPT_ENTRY(15) |
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[15519cb] | 247 | DISTINCT_INTERRUPT_ENTRY(16) |
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[6128a4a] | 248 | |
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[67a2288] | 249 | /* |
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| 250 | * routine used to initialize the IDT by default |
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| 251 | */ |
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[6128a4a] | 252 | |
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[67a2288] | 253 | PUBLIC (default_raw_idt_handler) |
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| 254 | PUBLIC (raw_idt_notify) |
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[6128a4a] | 255 | |
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[67a2288] | 256 | SYM (default_raw_idt_handler): |
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| 257 | pusha |
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| 258 | cld |
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[385212f] | 259 | mov esp, ebp |
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| 260 | andl $ - CPU_STACK_ALIGNMENT, esp |
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| 261 | call raw_idt_notify |
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| 262 | mov ebp, esp |
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[67a2288] | 263 | popa |
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| 264 | iret |
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[6128a4a] | 265 | |
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[eb562f2] | 266 | END_CODE |
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| 267 | |
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| 268 | END |
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