source: rtems/c/src/lib/libbsp/i386/shared/irq/irq.c @ 93fb8797

Last change on this file since 93fb8797 was 93fb8797, checked in by Chris Johns <chrisj@…>, on May 6, 2016 at 7:55:29 AM

i386/pc386: Fix interrupt support.

Fix the interrupt and stop the spurious interrupt from happening.

The fix moves the EOI to C code and cleans that functionality out
of the asm part of the ISR handler.

The code checks the ISR and IRR registers on the enable.

Only ack the master for a slave IRQ if the slave has no other pending
requests.

  • Property mode set to 100644
File size: 9.7 KB
Line 
1/*
2 *  This file contains the implementation of the function described in irq.h
3 */
4
5/*
6 *  Copyright (c) 2009 embedded brains GmbH
7 *  Copyright (C) 1998 valette@crf.canon.fr
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.org/license/LICENSE.
12 */
13
14#include <bsp.h>
15#include <bsp/irq.h>
16#include <bsp/irq-generic.h>
17
18#include <stdlib.h>
19#include <stdio.h>
20#include <inttypes.h>
21
22
23#include "elcr.h"
24
25/*
26 * pointer to the mask representing the additionnal irq vectors
27 * that must be disabled when a particular entry is activated.
28 * They will be dynamically computed from teh prioruty table given
29 * in BSP_rtems_irq_mngt_set();
30 * CAUTION : this table is accessed directly by interrupt routine
31 *           prologue.
32 */
33static rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_LINES_NUMBER];
34
35/*
36 * Stats of interrupts dispatched.
37 */
38static uint32_t irq_count[BSP_IRQ_VECTOR_NUMBER] = {0};
39static uint32_t spurious_count;
40
41/*
42 * Edge or level trigger interrupts.
43 */
44static enum intr_trigger irq_trigger[BSP_IRQ_LINES_NUMBER];
45
46/*-------------------------------------------------------------------------+
47| Cache for 1st and 2nd PIC IRQ line's mssk (enabled or disabled) register.
48+--------------------------------------------------------------------------*/
49/*
50 * lower byte is interrupt mask on the master PIC.
51 * while upper bits are interrupt on the slave PIC.
52 * This cache is initialized in ldseg.s
53 */
54static rtems_i8259_masks i8259a_cache = 0xFFFB;
55
56/*
57 * Print the stats.
58 */
59uint32_t BSP_irq_count_dump(FILE *f)
60{
61  uint32_t tot = 0;
62  int      i;
63 if ( !f )
64   f = stdout;
65 fprintf(f,"SPURIOUS: %9"PRIu32"\n", spurious_count);
66 for ( i = 0; i < BSP_IRQ_VECTOR_NUMBER; i++ ) {
67   char type = '-';
68   if (i < BSP_IRQ_LINES_NUMBER)
69     type = irq_trigger[i] == INTR_TRIGGER_EDGE ? 'E' : 'L';
70   tot += irq_count[i];
71   fprintf(f,"IRQ %2u: %c %9"PRIu32"\n", i, type, irq_count[i]);
72 }
73 return tot;
74}
75
76/*
77 * Is the IRQ valid?
78 */
79static inline bool BSP_i8259a_irq_valid(const rtems_irq_number irqLine)
80{
81  return ((int)irqLine >= BSP_IRQ_VECTOR_LOWEST_OFFSET) &&
82    ((int)irqLine <= BSP_IRQ_MAX_ON_i8259A);
83}
84
85/*
86 * Read the IRR register. The default.
87 */
88static inline uint8_t BSP_i8259a_irq_int_request_reg(uint32_t ioport)
89{
90  uint8_t isr;
91  inport_byte(ioport, isr);
92  return isr;
93}
94
95/*
96 * Read the ISR register. Keep the default of the IRR.
97 */
98static inline uint8_t BSP_i8259a_irq_in_service_reg(uint32_t ioport)
99{
100  uint8_t isr;
101  outport_byte(ioport, PIC_OCW3_SEL | PIC_OCW3_RR | PIC_OCW3_RIS);
102  inport_byte(ioport, isr);
103  outport_byte(ioport, PIC_OCW3_SEL | PIC_OCW3_RR);
104  return isr;
105}
106
107/*-------------------------------------------------------------------------+
108|         Function:  BSP_irq_disable_at_i8259a
109|      Description: Mask IRQ line in appropriate PIC chip.
110| Global Variables: i8259a_cache
111|        Arguments: vector_offset - number of IRQ line to mask.
112|          Returns: 0 is OK.
113+--------------------------------------------------------------------------*/
114static int BSP_irq_disable_at_i8259a(const rtems_irq_number irqLine)
115{
116  unsigned short        mask;
117  rtems_interrupt_level level;
118
119  rtems_interrupt_disable(level);
120
121  mask = 1 << irqLine;
122  i8259a_cache |= mask;
123
124  if (irqLine < 8)
125  {
126    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259a_cache & 0xff);
127  }
128  else
129  {
130    outport_byte(PIC_SLAVE_IMR_IO_PORT, (i8259a_cache >> 8) & 0xff);
131  }
132
133  rtems_interrupt_enable(level);
134
135  return 0;
136}
137
138/*-------------------------------------------------------------------------+
139|         Function:  BSP_irq_enable_at_i8259a
140|      Description: Unmask IRQ line in appropriate PIC chip.
141| Global Variables: i8259a_cache
142|        Arguments: irqLine - number of IRQ line to mask.
143|          Returns: Nothing.
144+--------------------------------------------------------------------------*/
145static int BSP_irq_enable_at_i8259a(const rtems_irq_number irqLine)
146{
147  unsigned short        mask;
148  rtems_interrupt_level level;
149  uint8_t               isr;
150  uint8_t               irr;
151
152  rtems_interrupt_disable(level);
153
154  mask = 1 << irqLine;
155  i8259a_cache &= ~mask;
156
157  if (irqLine < 8)
158  {
159    isr = BSP_i8259a_irq_in_service_reg(PIC_MASTER_COMMAND_IO_PORT);
160    irr = BSP_i8259a_irq_int_request_reg(PIC_MASTER_COMMAND_IO_PORT);
161    outport_byte(PIC_MASTER_IMR_IO_PORT, i8259a_cache & 0xff);
162  }
163  else
164  {
165    isr = BSP_i8259a_irq_in_service_reg(PIC_SLAVE_COMMAND_IO_PORT);
166    irr = BSP_i8259a_irq_int_request_reg(PIC_SLAVE_COMMAND_IO_PORT);
167    outport_byte(PIC_SLAVE_IMR_IO_PORT, (i8259a_cache >> 8) & 0xff);
168  }
169
170  if (((isr ^ irr) & mask) != 0)
171    printk("i386: isr=%x irr=%x\n", isr, irr);
172
173  rtems_interrupt_enable(level);
174
175  return 0;
176} /* mask_irq */
177
178/*-------------------------------------------------------------------------+
179|         Function: BSP_irq_ack_at_i8259a
180|      Description: Signal generic End Of Interrupt (EOI) to appropriate PIC.
181| Global Variables: None.
182|        Arguments: irqLine - number of IRQ line to acknowledge.
183|          Returns: Nothing.
184+--------------------------------------------------------------------------*/
185static int BSP_irq_ack_at_i8259a(const rtems_irq_number irqLine)
186{
187  uint8_t slave_isr = 0;
188
189  if (irqLine >= 8) {
190   outport_byte(PIC_SLAVE_COMMAND_IO_PORT, PIC_EOI);
191   slave_isr = BSP_i8259a_irq_in_service_reg(PIC_SLAVE_COMMAND_IO_PORT);
192  }
193
194  /*
195   * Only issue the EOI to the master if there are no more interrupts in
196   * service for the slave. i8259a data sheet page 18, The Special Fully Nested
197   * Mode, b.
198   */
199  if (slave_isr == 0)
200    outport_byte(PIC_MASTER_COMMAND_IO_PORT, PIC_EOI);
201
202  return 0;
203
204} /* ackIRQ */
205
206/*
207 * ------------------------ RTEMS Irq helper functions ----------------
208 */
209
210static rtems_irq_prio irqPrioTable[BSP_IRQ_LINES_NUMBER]={
211  /*
212   * actual priorities for each interrupt source:
213   *    0   means that only current interrupt is masked
214   *    255 means all other interrupts are masked
215   * The second entry has a priority of 255 because
216   * it is the slave pic entry and is should always remain
217   * unmasked.
218   */
219  0,0,
220  255,
221  0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0
222};
223
224static void compute_i8259_masks_from_prio (void)
225{
226  rtems_interrupt_level level;
227  unsigned int i;
228  unsigned int j;
229
230  rtems_interrupt_disable(level);
231
232  /*
233   * Always mask at least current interrupt to prevent re-entrance
234   */
235  for (i=0; i < BSP_IRQ_LINES_NUMBER; i++) {
236    * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
237    for (j = 0; j < BSP_IRQ_LINES_NUMBER; j++) {
238      /*
239       * Mask interrupts at i8259 level that have a lower priority
240       */
241      if (irqPrioTable [i] > irqPrioTable [j]) {
242        * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j);
243      }
244    }
245  }
246
247  rtems_interrupt_enable(level);
248}
249
250static inline bool bsp_interrupt_vector_is_valid(rtems_vector_number vector)
251{
252  return BSP_i8259a_irq_valid((const rtems_irq_number) vector);
253}
254
255rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
256{
257  if (bsp_interrupt_vector_is_valid(vector))
258    BSP_irq_enable_at_i8259a(vector);
259  return RTEMS_SUCCESSFUL;
260}
261
262rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
263{
264  if (bsp_interrupt_vector_is_valid(vector))
265    BSP_irq_disable_at_i8259a(vector);
266  return RTEMS_SUCCESSFUL;
267}
268
269rtems_status_code bsp_interrupt_facility_initialize(void)
270{
271  int i;
272
273  /*
274   * set up internal tables used by rtems interrupt prologue
275   */
276  compute_i8259_masks_from_prio();
277
278  /*
279   * must enable slave pic anyway
280   */
281  BSP_irq_enable_at_i8259a(2);
282
283  /*
284   * Probe the ELCR.
285   */
286  elcr_probe();
287
288  for (i = 0; i < BSP_IRQ_LINES_NUMBER; i++)
289    irq_trigger[i] = elcr_read_trigger(i);
290
291  return RTEMS_SUCCESSFUL;
292}
293
294/*
295 * Global so the asm handler can call it.
296 */
297void BSP_dispatch_isr(int vector);
298
299void BSP_dispatch_isr(int vector)
300{
301  uint16_t old_imr = 0;
302
303  if (vector < BSP_IRQ_VECTOR_NUMBER) {
304    /*
305     * Hardware?
306     */
307    if (vector <= BSP_IRQ_MAX_ON_i8259A) {
308      /*
309       * See if this is a spurious interrupt.
310       */
311      if ((vector == 7 || vector == 15)) {
312        /*
313         * Only check it there no handler for 7 or 15.
314         */
315        if (bsp_interrupt_handler_is_empty(vector)) {
316          /*
317           * Read the ISR register to see if IRQ 7/15 is really pending.
318           */
319          uint8_t isr = BSP_i8259a_irq_in_service_reg(PIC_MASTER_COMMAND_IO_PORT);
320          if ((isr & (1 << 7)) == 0) {
321            ++spurious_count;
322            return;
323          }
324        }
325      }
326
327      /*
328       * Save the current cached value for the IMR. It will have the bit for this
329       * vector clear.
330       */
331      if (vector <= BSP_IRQ_MAX_ON_i8259A) {
332        old_imr = i8259a_cache;
333        i8259a_cache |= irq_mask_or_tbl[vector];
334        outport_byte(PIC_MASTER_IMR_IO_PORT, i8259a_cache & 0xff);
335        outport_byte(PIC_SLAVE_IMR_IO_PORT, (i8259a_cache >> 8) & 0xff);
336      }
337
338      /*
339       * Do not use auto-EOI as some slave PIC do not work correctly.
340       */
341      BSP_irq_ack_at_i8259a(vector);
342    }
343
344    /*
345     * Count the interrupt.
346     */
347    irq_count[vector]++;
348
349    /*
350     * Allow nesting.
351     */
352    __asm__ __volatile__("sti");
353
354    bsp_interrupt_handler_dispatch(vector);
355
356    /*
357     * Disallow nesting.
358     */
359    __asm__ __volatile__("cli");
360
361    if (vector <= BSP_IRQ_MAX_ON_i8259A) {
362      /*
363       * Put the mask back but keep this vector masked if the trigger type is
364       * level. The driver or a thread level interrupt server needs to enable it
365       * again.
366       */
367      if (vector <= BSP_IRQ_MAX_ON_i8259A) {
368        if (irq_trigger[vector] == INTR_TRIGGER_LEVEL)
369          old_imr |= 1 << vector;
370        i8259a_cache = old_imr;
371        outport_byte(PIC_MASTER_IMR_IO_PORT, i8259a_cache & 0xff);
372        outport_byte(PIC_SLAVE_IMR_IO_PORT, (i8259a_cache >> 8) & 0xff);
373      }
374    }
375  }
376}
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