1 | /* irq.c |
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2 | * |
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3 | * This file contains the implementation of the function described in irq.h |
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4 | * |
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5 | * CopyRight (C) 1998 valette@crf.canon.fr |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | * |
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11 | * $Id$ |
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12 | */ |
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13 | |
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14 | #include <bsp.h> |
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15 | #include <bsp/irq.h> |
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16 | #include <rtems/score/thread.h> |
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17 | #include <rtems/score/apiext.h> |
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18 | |
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19 | /* |
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20 | * pointer to the mask representing the additionnal irq vectors |
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21 | * that must be disabled when a particular entry is activated. |
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22 | * They will be dynamically computed from teh prioruty table given |
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23 | * in BSP_rtems_irq_mngt_set(); |
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24 | * CAUTION : this table is accessed directly by interrupt routine |
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25 | * prologue. |
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26 | */ |
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27 | rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_LINES_NUMBER]; |
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28 | |
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29 | /* |
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30 | * default handler connected on each irq after bsp initialization |
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31 | */ |
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32 | static rtems_irq_connect_data default_rtems_entry; |
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33 | |
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34 | /* |
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35 | * location used to store initial tables used for interrupt |
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36 | * management. |
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37 | */ |
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38 | static rtems_irq_global_settings* internal_config; |
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39 | rtems_irq_connect_data* rtems_hdl_tbl; |
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40 | /*-------------------------------------------------------------------------+ |
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41 | | Cache for 1st and 2nd PIC IRQ line's status (enabled or disabled) register. |
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42 | +--------------------------------------------------------------------------*/ |
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43 | /* |
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44 | * lower byte is interrupt mask on the master PIC. |
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45 | * while upper bits are interrupt on the slave PIC. |
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46 | * This cache is initialized in ldseg.s |
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47 | */ |
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48 | rtems_i8259_masks i8259s_cache = 0xFFFB; |
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49 | |
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50 | /*-------------------------------------------------------------------------+ |
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51 | | Function: BSP_irq_disable_at_i8259s |
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52 | | Description: Mask IRQ line in appropriate PIC chip. |
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53 | | Global Variables: i8259s_cache |
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54 | | Arguments: vector_offset - number of IRQ line to mask. |
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55 | | Returns: Nothing. |
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56 | +--------------------------------------------------------------------------*/ |
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57 | int BSP_irq_disable_at_i8259s (const rtems_irq_symbolic_name irqLine) |
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58 | { |
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59 | unsigned short mask; |
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60 | unsigned int level; |
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61 | |
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62 | if ( ((int)irqLine < BSP_LOWEST_OFFSET) || |
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63 | ((int)irqLine > BSP_MAX_OFFSET ) |
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64 | ) |
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65 | return 1; |
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66 | |
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67 | _CPU_ISR_Disable(level); |
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68 | |
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69 | mask = 1 << irqLine; |
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70 | i8259s_cache |= mask; |
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71 | |
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72 | if (irqLine < 8) |
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73 | { |
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74 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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75 | } |
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76 | else |
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77 | { |
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78 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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79 | } |
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80 | _CPU_ISR_Enable (level); |
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81 | |
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82 | return 0; |
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83 | } |
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84 | |
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85 | /*-------------------------------------------------------------------------+ |
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86 | | Function: BSP_irq_enable_at_i8259s |
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87 | | Description: Unmask IRQ line in appropriate PIC chip. |
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88 | | Global Variables: i8259s_cache |
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89 | | Arguments: irqLine - number of IRQ line to mask. |
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90 | | Returns: Nothing. |
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91 | +--------------------------------------------------------------------------*/ |
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92 | int BSP_irq_enable_at_i8259s (const rtems_irq_symbolic_name irqLine) |
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93 | { |
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94 | unsigned short mask; |
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95 | unsigned int level; |
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96 | |
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97 | if ( ((int)irqLine < BSP_LOWEST_OFFSET) || |
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98 | ((int)irqLine > BSP_MAX_OFFSET ) |
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99 | ) |
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100 | return 1; |
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101 | |
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102 | _CPU_ISR_Disable(level); |
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103 | |
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104 | mask = ~(1 << irqLine); |
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105 | i8259s_cache &= mask; |
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106 | |
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107 | if (irqLine < 8) |
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108 | { |
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109 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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110 | } |
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111 | else |
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112 | { |
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113 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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114 | } |
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115 | _CPU_ISR_Enable (level); |
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116 | |
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117 | return 0; |
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118 | } /* mask_irq */ |
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119 | |
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120 | int BSP_irq_enabled_at_i8259s (const rtems_irq_symbolic_name irqLine) |
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121 | { |
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122 | unsigned short mask; |
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123 | |
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124 | if ( ((int)irqLine < BSP_LOWEST_OFFSET) || |
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125 | ((int)irqLine > BSP_MAX_OFFSET ) |
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126 | ) |
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127 | return 1; |
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128 | |
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129 | mask = (1 << irqLine); |
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130 | return (~(i8259s_cache & mask)); |
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131 | } |
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132 | |
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133 | /*-------------------------------------------------------------------------+ |
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134 | | Function: BSP_irq_ack_at_i8259s |
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135 | | Description: Signal generic End Of Interrupt (EOI) to appropriate PIC. |
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136 | | Global Variables: None. |
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137 | | Arguments: irqLine - number of IRQ line to acknowledge. |
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138 | | Returns: Nothing. |
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139 | +--------------------------------------------------------------------------*/ |
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140 | int BSP_irq_ack_at_i8259s (const rtems_irq_symbolic_name irqLine) |
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141 | { |
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142 | if ( ((int)irqLine < BSP_LOWEST_OFFSET) || |
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143 | ((int)irqLine > BSP_MAX_OFFSET ) |
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144 | ) |
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145 | return 1; |
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146 | |
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147 | if (irqLine >= 8) { |
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148 | outport_byte(PIC_SLAVE_COMMAND_IO_PORT, PIC_EOI); |
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149 | } |
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150 | outport_byte(PIC_MASTER_COMMAND_IO_PORT, PIC_EOI); |
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151 | |
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152 | return 0; |
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153 | |
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154 | } /* ackIRQ */ |
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155 | |
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156 | /* |
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157 | * ------------------------ RTEMS Irq helper functions ---------------- |
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158 | */ |
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159 | |
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160 | /* |
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161 | * Caution : this function assumes the variable "internal_config" |
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162 | * is already set and that the tables it contains are still valid |
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163 | * and accessible. |
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164 | */ |
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165 | static void compute_i8259_masks_from_prio () |
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166 | { |
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167 | unsigned int i; |
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168 | unsigned int j; |
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169 | /* |
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170 | * Always mask at least current interrupt to prevent re-entrance |
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171 | */ |
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172 | for (i=0; i < internal_config->irqNb; i++) { |
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173 | * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i); |
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174 | for (j = 0; j < internal_config->irqNb; j++) { |
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175 | /* |
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176 | * Mask interrupts at i8259 level that have a lower priority |
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177 | */ |
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178 | if (internal_config->irqPrioTbl [i] > internal_config->irqPrioTbl [j]) { |
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179 | * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j); |
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180 | } |
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181 | } |
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182 | } |
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183 | } |
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184 | |
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185 | /* |
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186 | * This function check that the value given for the irq line |
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187 | * is valid. |
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188 | */ |
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189 | |
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190 | static int isValidInterrupt(int irq) |
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191 | { |
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192 | if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET)) |
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193 | return 0; |
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194 | return 1; |
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195 | } |
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196 | |
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197 | /* |
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198 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
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199 | */ |
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200 | |
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201 | int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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202 | { |
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203 | unsigned int level; |
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204 | |
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205 | if (!isValidInterrupt(irq->name)) { |
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206 | return 0; |
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207 | } |
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208 | /* |
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209 | * Check if default handler is actually connected. If not issue an error. |
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210 | * You must first get the current handler via i386_get_current_idt_entry |
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211 | * and then disconnect it using i386_delete_idt_entry. |
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212 | * RATIONALE : to always have the same transition by forcing the user |
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213 | * to get the previous handler before accepting to disconnect. |
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214 | */ |
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215 | _CPU_ISR_Disable(level); |
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216 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
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217 | _CPU_ISR_Enable(level); |
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218 | return 0; |
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219 | } |
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220 | |
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221 | /* |
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222 | * store the data provided by user |
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223 | */ |
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224 | rtems_hdl_tbl[irq->name] = *irq; |
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225 | /* |
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226 | * Enable interrupt at PIC level |
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227 | */ |
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228 | BSP_irq_enable_at_i8259s (irq->name); |
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229 | /* |
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230 | * Enable interrupt on device |
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231 | */ |
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232 | irq->on(irq); |
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233 | |
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234 | _CPU_ISR_Enable(level); |
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235 | |
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236 | return 1; |
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237 | } |
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238 | |
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239 | int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
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240 | { |
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241 | unsigned int level; |
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242 | |
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243 | if (!isValidInterrupt(irq->name)) { |
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244 | return 0; |
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245 | } |
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246 | _CPU_ISR_Disable(level); |
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247 | *irq = rtems_hdl_tbl[irq->name]; |
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248 | _CPU_ISR_Enable(level); |
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249 | return 1; |
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250 | } |
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251 | |
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252 | int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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253 | { |
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254 | unsigned int level; |
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255 | |
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256 | if (!isValidInterrupt(irq->name)) { |
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257 | return 0; |
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258 | } |
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259 | /* |
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260 | * Check if default handler is actually connected. If not issue an error. |
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261 | * You must first get the current handler via i386_get_current_idt_entry |
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262 | * and then disconnect it using i386_delete_idt_entry. |
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263 | * RATIONALE : to always have the same transition by forcing the user |
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264 | * to get the previous handler before accepting to disconnect. |
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265 | */ |
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266 | _CPU_ISR_Disable(level); |
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267 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
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268 | _CPU_ISR_Enable(level); |
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269 | return 0; |
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270 | } |
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271 | |
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272 | /* |
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273 | * disable interrupt at PIC level |
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274 | */ |
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275 | BSP_irq_disable_at_i8259s (irq->name); |
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276 | |
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277 | /* |
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278 | * Disable interrupt on device |
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279 | */ |
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280 | irq->off(irq); |
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281 | |
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282 | /* |
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283 | * restore the default irq value |
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284 | */ |
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285 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
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286 | |
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287 | _CPU_ISR_Enable(level); |
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288 | |
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289 | return 1; |
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290 | } |
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291 | |
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292 | /* |
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293 | * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- |
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294 | */ |
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295 | |
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296 | int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) |
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297 | { |
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298 | int i; |
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299 | unsigned int level; |
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300 | /* |
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301 | * Store various code accelerators |
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302 | */ |
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303 | internal_config = config; |
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304 | default_rtems_entry = config->defaultEntry; |
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305 | rtems_hdl_tbl = config->irqHdlTbl; |
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306 | |
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307 | _CPU_ISR_Disable(level); |
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308 | /* |
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309 | * set up internal tables used by rtems interrupt prologue |
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310 | */ |
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311 | compute_i8259_masks_from_prio (); |
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312 | |
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313 | for (i=0; i < internal_config->irqNb; i++) { |
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314 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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315 | BSP_irq_enable_at_i8259s (i); |
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316 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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317 | } |
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318 | else { |
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319 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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320 | BSP_irq_disable_at_i8259s (i); |
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321 | } |
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322 | } |
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323 | /* |
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324 | * must enable slave pic anyway |
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325 | */ |
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326 | BSP_irq_enable_at_i8259s (2); |
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327 | _CPU_ISR_Enable(level); |
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328 | return 1; |
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329 | } |
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330 | |
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331 | int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
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332 | { |
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333 | *config = internal_config; |
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334 | return 0; |
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335 | } |
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336 | |
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337 | void _ThreadProcessSignalsFromIrq (CPU_Exception_frame* ctx) |
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338 | { |
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339 | /* |
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340 | * Process pending signals that have not already been |
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341 | * processed by _Thread_Displatch. This happens quite |
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342 | * unfrequently : the ISR must have posted an action |
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343 | * to the current running thread. |
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344 | */ |
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345 | if ( _Thread_Do_post_task_switch_extension || |
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346 | _Thread_Executing->do_post_task_switch_extension ) { |
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347 | _Thread_Executing->do_post_task_switch_extension = FALSE; |
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348 | _API_extensions_Run_postswitch(); |
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349 | } |
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350 | /* |
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351 | * I plan to process other thread related events here. |
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352 | * This will include DEBUG session requested from keyboard... |
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353 | */ |
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354 | } |
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355 | |
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356 | void processIrq(unsigned index) |
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357 | { |
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358 | rtems_hdl_tbl[index].hdl(rtems_hdl_tbl[index].handle); |
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359 | } |
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360 | |
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