source: rtems/c/src/lib/libbsp/i386/shared/irq/irq.c @ 6b54dcb

Last change on this file since 6b54dcb was 6b54dcb, checked in by Pavel Pisa <pisa@…>, on Oct 12, 2016 at 7:40:41 AM

bsps/i386: replace global interrupt disable by SMP build supporting locking.

  • Property mode set to 100644
File size: 10.8 KB
Line 
1/*
2 *  This file contains the implementation of the function described in irq.h
3 */
4
5/*
6 *  Copyright (c) 2009 embedded brains GmbH
7 *  Copyright (C) 1998 valette@crf.canon.fr
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.org/license/LICENSE.
12 */
13
14#include <bsp.h>
15#include <bsp/irq.h>
16#include <bsp/irq-generic.h>
17#include <rtems/score/cpu.h>
18
19#include <stdlib.h>
20#include <stdio.h>
21#include <inttypes.h>
22
23
24#include "elcr.h"
25
26RTEMS_INTERRUPT_LOCK_DEFINE( static, rtems_i8259_access_lock, "rtems_i8259_access_lock" );
27
28/*
29 * pointer to the mask representing the additionnal irq vectors
30 * that must be disabled when a particular entry is activated.
31 * They will be dynamically computed from teh prioruty table given
32 * in BSP_rtems_irq_mngt_set();
33 * CAUTION : this table is accessed directly by interrupt routine
34 *           prologue.
35 */
36static rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_LINES_NUMBER];
37
38/*
39 * Stats of interrupts dispatched.
40 */
41static uint32_t irq_count[BSP_IRQ_VECTOR_NUMBER] = {0};
42static uint32_t spurious_count;
43
44/*
45 * Edge or level trigger interrupts.
46 */
47static enum intr_trigger irq_trigger[BSP_IRQ_LINES_NUMBER];
48
49/*-------------------------------------------------------------------------+
50| Cache for 1st and 2nd PIC IRQ line's mssk (enabled or disabled) register.
51+--------------------------------------------------------------------------*/
52/*
53 * lower byte is interrupt mask on the master PIC.
54 * while upper bits are interrupt on the slave PIC.
55 * This cache is initialized in ldseg.s
56 */
57static rtems_i8259_masks i8259a_imr_cache = 0xFFFB;
58static rtems_i8259_masks i8259a_in_progress = 0;
59
60static inline
61void BSP_i8259a_irq_update_master_imr( void )
62{
63  rtems_i8259_masks mask = i8259a_in_progress | i8259a_imr_cache;
64  outport_byte( PIC_MASTER_IMR_IO_PORT, mask & 0xff );
65}
66
67static inline
68void BSP_i8259a_irq_update_slave_imr( void )
69{
70  rtems_i8259_masks mask = i8259a_in_progress | i8259a_imr_cache;
71  outport_byte( PIC_SLAVE_IMR_IO_PORT, ( mask >> 8 ) & 0xff );
72}
73
74/*
75 * Print the stats.
76 */
77uint32_t BSP_irq_count_dump(FILE *f)
78{
79  uint32_t tot = 0;
80  int      i;
81 if ( !f )
82   f = stdout;
83 fprintf(f,"SPURIOUS: %9"PRIu32"\n", spurious_count);
84 for ( i = 0; i < BSP_IRQ_VECTOR_NUMBER; i++ ) {
85   char type = '-';
86   if (i < BSP_IRQ_LINES_NUMBER)
87     type = irq_trigger[i] == INTR_TRIGGER_EDGE ? 'E' : 'L';
88   tot += irq_count[i];
89   fprintf(f,"IRQ %2u: %c %9"PRIu32"\n", i, type, irq_count[i]);
90 }
91 return tot;
92}
93
94/*
95 * Is the IRQ valid?
96 */
97static inline bool BSP_i8259a_irq_valid(const rtems_irq_number irqLine)
98{
99  return ((int)irqLine >= BSP_IRQ_VECTOR_LOWEST_OFFSET) &&
100    ((int)irqLine <= BSP_IRQ_MAX_ON_i8259A);
101}
102
103/*
104 * Read the IRR register. The default.
105 */
106static inline uint8_t BSP_i8259a_irq_int_request_reg(uint32_t ioport)
107{
108  uint8_t isr;
109  inport_byte(ioport, isr);
110  return isr;
111}
112
113/*
114 * Read the ISR register. Keep the default of the IRR.
115 */
116static inline uint8_t BSP_i8259a_irq_in_service_reg(uint32_t ioport)
117{
118  uint8_t isr;
119  outport_byte(ioport, PIC_OCW3_SEL | PIC_OCW3_RR | PIC_OCW3_RIS);
120  inport_byte(ioport, isr);
121  outport_byte(ioport, PIC_OCW3_SEL | PIC_OCW3_RR);
122  return isr;
123}
124
125/*-------------------------------------------------------------------------+
126|         Function:  BSP_irq_disable_at_i8259a
127|      Description: Mask IRQ line in appropriate PIC chip.
128| Global Variables: i8259a_imr_cache, i8259a_in_progress
129|        Arguments: vector_offset - number of IRQ line to mask.
130|          Returns: 0 is OK.
131+--------------------------------------------------------------------------*/
132static int BSP_irq_disable_at_i8259a(const rtems_irq_number irqLine)
133{
134  unsigned short        mask;
135  rtems_interrupt_lock_context lock_context;
136
137  rtems_interrupt_lock_acquire(&rtems_i8259_access_lock, &lock_context);
138
139  mask = 1 << irqLine;
140  i8259a_imr_cache |= mask;
141
142  if (irqLine < 8)
143  {
144    BSP_i8259a_irq_update_master_imr();
145  }
146  else
147  {
148    BSP_i8259a_irq_update_slave_imr();
149  }
150
151  rtems_interrupt_lock_release(&rtems_i8259_access_lock, &lock_context);
152
153  return 0;
154}
155
156/*-------------------------------------------------------------------------+
157|         Function:  BSP_irq_enable_at_i8259a
158|      Description: Unmask IRQ line in appropriate PIC chip.
159| Global Variables: i8259a_imr_cache, i8259a_in_progress
160|        Arguments: irqLine - number of IRQ line to mask.
161|          Returns: Nothing.
162+--------------------------------------------------------------------------*/
163static int BSP_irq_enable_at_i8259a(const rtems_irq_number irqLine)
164{
165  unsigned short        mask;
166  rtems_interrupt_lock_context lock_context;
167  uint8_t               isr;
168  uint8_t               irr;
169
170  rtems_interrupt_lock_acquire(&rtems_i8259_access_lock, &lock_context);
171
172  mask = 1 << irqLine;
173  i8259a_imr_cache &= ~mask;
174
175  if (irqLine < 8)
176  {
177    isr = BSP_i8259a_irq_in_service_reg(PIC_MASTER_COMMAND_IO_PORT);
178    irr = BSP_i8259a_irq_int_request_reg(PIC_MASTER_COMMAND_IO_PORT);
179    BSP_i8259a_irq_update_master_imr();
180  }
181  else
182  {
183    isr = BSP_i8259a_irq_in_service_reg(PIC_SLAVE_COMMAND_IO_PORT);
184    irr = BSP_i8259a_irq_int_request_reg(PIC_SLAVE_COMMAND_IO_PORT);
185    BSP_i8259a_irq_update_slave_imr();
186  }
187
188  if (((isr ^ irr) & mask) != 0)
189    printk("i386: isr=%x irr=%x\n", isr, irr);
190
191  rtems_interrupt_lock_release(&rtems_i8259_access_lock, &lock_context);
192
193  return 0;
194} /* mask_irq */
195
196/*-------------------------------------------------------------------------+
197|         Function: BSP_irq_ack_at_i8259a
198|      Description: Signal generic End Of Interrupt (EOI) to appropriate PIC.
199| Global Variables: None.
200|        Arguments: irqLine - number of IRQ line to acknowledge.
201|          Returns: Nothing.
202+--------------------------------------------------------------------------*/
203static int BSP_irq_ack_at_i8259a(const rtems_irq_number irqLine)
204{
205  uint8_t slave_isr = 0;
206
207  if (irqLine >= 8) {
208   outport_byte(PIC_SLAVE_COMMAND_IO_PORT, PIC_EOI);
209   slave_isr = BSP_i8259a_irq_in_service_reg(PIC_SLAVE_COMMAND_IO_PORT);
210  }
211
212  /*
213   * Only issue the EOI to the master if there are no more interrupts in
214   * service for the slave. i8259a data sheet page 18, The Special Fully Nested
215   * Mode, b.
216   */
217  if (slave_isr == 0)
218    outport_byte(PIC_MASTER_COMMAND_IO_PORT, PIC_EOI);
219
220  return 0;
221
222} /* ackIRQ */
223
224/*
225 * ------------------------ RTEMS Irq helper functions ----------------
226 */
227
228static rtems_irq_prio irqPrioTable[BSP_IRQ_LINES_NUMBER]={
229  /*
230   * actual priorities for each interrupt source:
231   *    0   means that only current interrupt is masked
232   *    255 means all other interrupts are masked
233   * The second entry has a priority of 255 because
234   * it is the slave pic entry and is should always remain
235   * unmasked.
236   */
237  0,0,
238  255,
239  0, 0, 0, 0,  0,  0,  0,  0,  0,  0,  0,  0
240};
241
242static void compute_i8259_masks_from_prio (void)
243{
244  rtems_interrupt_lock_context lock_context;
245  unsigned int i;
246  unsigned int j;
247
248  rtems_interrupt_lock_acquire(&rtems_i8259_access_lock, &lock_context);
249
250  /*
251   * Always mask at least current interrupt to prevent re-entrance
252   */
253  for (i=0; i < BSP_IRQ_LINES_NUMBER; i++) {
254    * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
255    for (j = 0; j < BSP_IRQ_LINES_NUMBER; j++) {
256      /*
257       * Mask interrupts at i8259 level that have a lower priority
258       */
259      if (irqPrioTable [i] > irqPrioTable [j]) {
260        * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j);
261      }
262    }
263  }
264
265  rtems_interrupt_lock_release(&rtems_i8259_access_lock, &lock_context);
266}
267
268static inline bool bsp_interrupt_vector_is_valid(rtems_vector_number vector)
269{
270  return BSP_i8259a_irq_valid((const rtems_irq_number) vector);
271}
272
273rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
274{
275  if (bsp_interrupt_vector_is_valid(vector))
276    BSP_irq_enable_at_i8259a(vector);
277  return RTEMS_SUCCESSFUL;
278}
279
280rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
281{
282  if (bsp_interrupt_vector_is_valid(vector))
283    BSP_irq_disable_at_i8259a(vector);
284  return RTEMS_SUCCESSFUL;
285}
286
287rtems_status_code bsp_interrupt_facility_initialize(void)
288{
289  int i;
290
291  /*
292   * set up internal tables used by rtems interrupt prologue
293   */
294  compute_i8259_masks_from_prio();
295
296  /*
297   * must enable slave pic anyway
298   */
299  BSP_irq_enable_at_i8259a(2);
300
301  /*
302   * Probe the ELCR.
303   */
304  elcr_probe();
305
306  for (i = 0; i < BSP_IRQ_LINES_NUMBER; i++)
307    irq_trigger[i] = elcr_read_trigger(i);
308
309  return RTEMS_SUCCESSFUL;
310}
311
312/*
313 * Global so the asm handler can call it.
314 */
315void BSP_dispatch_isr(int vector);
316
317void BSP_dispatch_isr(int vector)
318{
319  rtems_interrupt_lock_context lock_context;
320  rtems_i8259_masks in_progress_save = 0;
321
322  if (vector < BSP_IRQ_VECTOR_NUMBER) {
323    /*
324     * Hardware?
325     */
326    if (vector <= BSP_IRQ_MAX_ON_i8259A) {
327
328      rtems_interrupt_lock_acquire_isr(&rtems_i8259_access_lock, &lock_context);
329
330      /*
331       * See if this is a spurious interrupt.
332       */
333      if ((vector == 7 || vector == 15)) {
334        /*
335         * Only check it there no handler for 7 or 15.
336         */
337        if (bsp_interrupt_handler_is_empty(vector)) {
338          /*
339           * Read the ISR register to see if IRQ 7/15 is really pending.
340           */
341          uint8_t isr = BSP_i8259a_irq_in_service_reg(PIC_MASTER_COMMAND_IO_PORT);
342          if ((isr & (1 << 7)) == 0) {
343            ++spurious_count;
344            rtems_interrupt_lock_release_isr(&rtems_i8259_access_lock, &lock_context);
345            return;
346          }
347        }
348      }
349
350      /*
351       * Save the current cached value for the IMR. It will have the bit for this
352       * vector clear.
353       */
354      if (vector <= BSP_IRQ_MAX_ON_i8259A) {
355        in_progress_save = i8259a_in_progress;
356        i8259a_in_progress |= irq_mask_or_tbl[vector];
357        BSP_i8259a_irq_update_master_imr();
358        BSP_i8259a_irq_update_slave_imr();
359      }
360
361      /*
362       * Do not use auto-EOI as some slave PIC do not work correctly.
363       */
364      BSP_irq_ack_at_i8259a(vector);
365
366      rtems_interrupt_lock_release_isr(&rtems_i8259_access_lock, &lock_context);
367    }
368
369    /*
370     * Count the interrupt.
371     */
372    irq_count[vector]++;
373
374    RTEMS_COMPILER_MEMORY_BARRIER();
375    /*
376     * Allow nesting.
377     */
378    __asm__ __volatile__("sti");
379
380    bsp_interrupt_handler_dispatch(vector);
381
382    /*
383     * Disallow nesting.
384     */
385    __asm__ __volatile__("cli");
386
387    RTEMS_COMPILER_MEMORY_BARRIER();
388
389    if (vector <= BSP_IRQ_MAX_ON_i8259A) {
390
391      rtems_interrupt_lock_acquire_isr(&rtems_i8259_access_lock, &lock_context);
392
393      /*
394       * Put the mask back but keep this vector masked if the trigger type is
395       * level. The driver or a thread level interrupt server needs to enable it
396       * again.
397       */
398      if (vector <= BSP_IRQ_MAX_ON_i8259A) {
399        i8259a_in_progress = in_progress_save;
400        BSP_i8259a_irq_update_master_imr();
401        BSP_i8259a_irq_update_slave_imr();
402      }
403
404      rtems_interrupt_lock_release_isr(&rtems_i8259_access_lock, &lock_context);
405    }
406  }
407}
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