1 | /* irq.c |
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2 | * |
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3 | * This file contains the implementation of the function described in irq.h |
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4 | * |
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5 | * CopyRight (C) 1998 valette@crf.canon.fr |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in found in the file LICENSE in this distribution or at |
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9 | * http://www.OARcorp.com/rtems/license.html. |
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10 | * |
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11 | * $Id$ |
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12 | */ |
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13 | |
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14 | |
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15 | #include <bsp.h> |
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16 | #include <irq.h> |
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17 | |
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18 | /* |
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19 | * pointer to the mask representing the additionnal irq vectors |
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20 | * that must be disabled when a particular entry is activated. |
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21 | * They will be dynamically computed from teh prioruty table given |
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22 | * in pc386_rtems_irq_mngt_set(); |
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23 | * CAUTION : this table is accessed directly by interrupt routine |
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24 | * prologue. |
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25 | */ |
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26 | rtems_i8259_masks irq_mask_or_tbl[PC_386_IRQ_LINES_NUMBER]; |
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27 | |
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28 | /* |
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29 | * Copy of data given via initial pc386_rtems_irq_mngt_set() for |
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30 | * the sake of efficiency. |
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31 | * CAUTION : this table is accessed directly by interrupt routine |
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32 | * prologue. |
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33 | */ |
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34 | rtems_irq_hdl current_irq[PC_386_IRQ_LINES_NUMBER]; |
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35 | /* |
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36 | * default handler connected on each irq after bsp initialization |
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37 | */ |
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38 | static rtems_irq_connect_data default_rtems_entry; |
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39 | |
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40 | /* |
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41 | * location used to store initial tables used for interrupt |
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42 | * management. |
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43 | */ |
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44 | static rtems_irq_global_settings* internal_config; |
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45 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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46 | /*-------------------------------------------------------------------------+ |
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47 | | Cache for 1st and 2nd PIC IRQ line's status (enabled or disabled) register. |
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48 | +--------------------------------------------------------------------------*/ |
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49 | /* |
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50 | * lower byte is interrupt mask on the master PIC. |
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51 | * while upper bits are interrupt on the slave PIC. |
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52 | * This cache is initialized in ldseg.s |
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53 | */ |
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54 | rtems_i8259_masks i8259s_cache; |
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55 | |
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56 | /*-------------------------------------------------------------------------+ |
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57 | | Function: PC386_irq_disable_at_i8259s |
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58 | | Description: Mask IRQ line in appropriate PIC chip. |
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59 | | Global Variables: i8259s_cache |
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60 | | Arguments: vector_offset - number of IRQ line to mask. |
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61 | | Returns: Nothing. |
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62 | +--------------------------------------------------------------------------*/ |
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63 | int pc386_irq_disable_at_i8259s (const rtems_irq_symbolic_name irqLine) |
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64 | { |
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65 | unsigned short mask; |
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66 | unsigned int level; |
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67 | |
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68 | if ( ((int)irqLine < PC_386_LOWEST_OFFSET) || |
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69 | ((int)irqLine > PC_386_MAX_OFFSET ) |
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70 | ) |
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71 | return 1; |
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72 | |
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73 | _CPU_ISR_Disable(level); |
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74 | |
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75 | mask = 1 << irqLine; |
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76 | i8259s_cache |= mask; |
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77 | |
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78 | if (irqLine < 8) |
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79 | { |
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80 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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81 | } |
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82 | else |
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83 | { |
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84 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8)); |
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85 | } |
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86 | _CPU_ISR_Enable (level); |
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87 | |
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88 | return 0; |
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89 | } |
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90 | |
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91 | /*-------------------------------------------------------------------------+ |
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92 | | Function: pc386_irq_enable_at_i8259s |
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93 | | Description: Unmask IRQ line in appropriate PIC chip. |
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94 | | Global Variables: i8259s_cache |
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95 | | Arguments: irqLine - number of IRQ line to mask. |
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96 | | Returns: Nothing. |
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97 | +--------------------------------------------------------------------------*/ |
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98 | int pc386_irq_enable_at_i8259s (const rtems_irq_symbolic_name irqLine) |
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99 | { |
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100 | unsigned short mask; |
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101 | unsigned int level; |
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102 | |
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103 | if ( ((int)irqLine < PC_386_LOWEST_OFFSET) || |
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104 | ((int)irqLine > PC_386_MAX_OFFSET ) |
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105 | ) |
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106 | return 1; |
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107 | |
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108 | _CPU_ISR_Disable(level); |
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109 | |
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110 | mask = ~(1 << irqLine); |
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111 | i8259s_cache &= mask; |
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112 | |
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113 | if (irqLine < 8) |
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114 | { |
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115 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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116 | } |
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117 | else |
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118 | { |
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119 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) > 8)); |
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120 | } |
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121 | _CPU_ISR_Enable (level); |
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122 | |
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123 | return 0; |
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124 | } /* mask_irq */ |
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125 | |
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126 | int pc386_irq_enabled_at_i8259s (const rtems_irq_symbolic_name irqLine) |
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127 | { |
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128 | unsigned short mask; |
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129 | |
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130 | if ( ((int)irqLine < PC_386_LOWEST_OFFSET) || |
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131 | ((int)irqLine > PC_386_MAX_OFFSET ) |
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132 | ) |
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133 | return 1; |
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134 | |
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135 | mask = (1 << irqLine); |
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136 | return (~(i8259s_cache & mask)); |
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137 | } |
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138 | |
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139 | |
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140 | /*-------------------------------------------------------------------------+ |
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141 | | Function: pc386_irq_ack_at_i8259s |
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142 | | Description: Signal generic End Of Interrupt (EOI) to appropriate PIC. |
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143 | | Global Variables: None. |
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144 | | Arguments: irqLine - number of IRQ line to acknowledge. |
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145 | | Returns: Nothing. |
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146 | +--------------------------------------------------------------------------*/ |
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147 | int pc386_irq_ack_at_i8259s (const rtems_irq_symbolic_name irqLine) |
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148 | { |
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149 | if ( ((int)irqLine < PC_386_LOWEST_OFFSET) || |
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150 | ((int)irqLine > PC_386_MAX_OFFSET ) |
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151 | ) |
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152 | return 1; |
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153 | |
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154 | if (irqLine >= 8) { |
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155 | outport_byte(PIC_SLAVE_COMMAND_IO_PORT, PIC_EOI); |
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156 | } |
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157 | outport_byte(PIC_MASTER_COMMAND_IO_PORT, PIC_EOI); |
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158 | |
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159 | return 0; |
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160 | |
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161 | } /* ackIRQ */ |
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162 | |
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163 | /* |
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164 | * ------------------------ RTEMS Irq helper functions ---------------- |
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165 | */ |
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166 | |
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167 | /* |
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168 | * Caution : this function assumes the variable "internal_config" |
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169 | * is already set and that the tables it contains are still valid |
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170 | * and accessible. |
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171 | */ |
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172 | static void compute_i8259_masks_from_prio () |
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173 | { |
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174 | unsigned int i; |
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175 | unsigned int j; |
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176 | /* |
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177 | * Always mask at least current interrupt to prevent re-entrance |
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178 | */ |
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179 | for (i=0; i < internal_config->irqNb; i++) { |
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180 | * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i); |
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181 | for (j = 0; j < internal_config->irqNb; j++) { |
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182 | /* |
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183 | * Mask interrupts at i8259 level that have a lower priority |
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184 | */ |
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185 | if (internal_config->irqPrioTbl [i] > internal_config->irqPrioTbl [j]) { |
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186 | * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j); |
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187 | } |
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188 | } |
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189 | } |
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190 | } |
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191 | |
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192 | /* |
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193 | * Caution : this function assumes the variable "internal_config" |
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194 | * is already set and that the tables it contains are still valid |
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195 | * and accessible. |
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196 | */ |
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197 | static void make_copy_of_handlers () |
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198 | { |
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199 | int i; |
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200 | for (i=0; i < internal_config->irqNb; i++) { |
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201 | current_irq [i] = internal_config->irqHdlTbl[i].hdl; |
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202 | } |
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203 | } |
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204 | |
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205 | |
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206 | /* |
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207 | * This function check that the value given for the irq line |
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208 | * is valid. |
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209 | */ |
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210 | |
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211 | static int isValidInterrupt(int irq) |
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212 | { |
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213 | if ( (irq < PC_386_LOWEST_OFFSET) || (irq > PC_386_MAX_OFFSET)) |
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214 | return 0; |
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215 | return 1; |
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216 | } |
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217 | |
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218 | /* |
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219 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
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220 | */ |
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221 | |
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222 | int pc386_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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223 | { |
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224 | unsigned int level; |
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225 | |
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226 | if (!isValidInterrupt(irq->name)) { |
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227 | return 0; |
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228 | } |
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229 | /* |
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230 | * Check if default handler is actually connected. If not issue an error. |
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231 | * You must first get the current handler via i386_get_current_idt_entry |
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232 | * and then disconnect it using i386_delete_idt_entry. |
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233 | * RATIONALE : to always have the same transition by forcing the user |
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234 | * to get the previous handler before accepting to disconnect. |
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235 | */ |
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236 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
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237 | return 0; |
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238 | } |
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239 | _CPU_ISR_Disable(level); |
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240 | |
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241 | /* |
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242 | * store the data provided by user |
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243 | */ |
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244 | rtems_hdl_tbl[irq->name] = *irq; |
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245 | /* |
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246 | * update table used directly by rtems interrupt prologue |
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247 | */ |
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248 | current_irq [irq->name] = irq->hdl; |
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249 | /* |
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250 | * Enable interrupt at PIC level |
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251 | */ |
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252 | pc386_irq_enable_at_i8259s (irq->name); |
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253 | /* |
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254 | * Enable interrupt on device |
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255 | */ |
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256 | irq->on(irq); |
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257 | |
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258 | _CPU_ISR_Enable(level); |
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259 | |
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260 | return 1; |
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261 | } |
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262 | |
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263 | |
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264 | int pc386_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
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265 | { |
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266 | if (!isValidInterrupt(irq->name)) { |
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267 | return 0; |
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268 | } |
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269 | *irq = rtems_hdl_tbl[irq->name]; |
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270 | return 1; |
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271 | } |
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272 | |
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273 | int pc386_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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274 | { |
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275 | unsigned int level; |
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276 | |
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277 | if (!isValidInterrupt(irq->name)) { |
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278 | return 0; |
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279 | } |
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280 | /* |
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281 | * Check if default handler is actually connected. If not issue an error. |
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282 | * You must first get the current handler via i386_get_current_idt_entry |
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283 | * and then disconnect it using i386_delete_idt_entry. |
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284 | * RATIONALE : to always have the same transition by forcing the user |
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285 | * to get the previous handler before accepting to disconnect. |
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286 | */ |
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287 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
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288 | return 0; |
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289 | } |
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290 | _CPU_ISR_Disable(level); |
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291 | |
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292 | /* |
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293 | * disable interrupt at PIC level |
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294 | */ |
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295 | pc386_irq_disable_at_i8259s (irq->name); |
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296 | |
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297 | /* |
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298 | * Disable interrupt on device |
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299 | */ |
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300 | irq->off(irq); |
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301 | |
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302 | /* |
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303 | * restore the default irq value |
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304 | */ |
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305 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
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306 | |
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307 | current_irq[irq->name] = default_rtems_entry.hdl; |
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308 | |
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309 | _CPU_ISR_Enable(level); |
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310 | |
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311 | return 1; |
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312 | } |
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313 | |
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314 | /* |
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315 | * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- |
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316 | */ |
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317 | |
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318 | int pc386_rtems_irq_mngt_set(rtems_irq_global_settings* config) |
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319 | { |
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320 | int i; |
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321 | unsigned int level; |
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322 | /* |
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323 | * Store various code accelerators |
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324 | */ |
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325 | internal_config = config; |
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326 | default_rtems_entry = config->defaultEntry; |
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327 | rtems_hdl_tbl = config->irqHdlTbl; |
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328 | |
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329 | _CPU_ISR_Disable(level); |
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330 | /* |
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331 | * set up internal tables used by rtems interrupt prologue |
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332 | */ |
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333 | compute_i8259_masks_from_prio (); |
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334 | make_copy_of_handlers (); |
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335 | |
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336 | for (i=0; i < internal_config->irqNb; i++) { |
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337 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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338 | pc386_irq_enable_at_i8259s (i); |
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339 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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340 | } |
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341 | else { |
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342 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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343 | pc386_irq_disable_at_i8259s (i); |
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344 | } |
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345 | } |
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346 | /* |
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347 | * must disable slave pic anyway |
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348 | */ |
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349 | pc386_irq_enable_at_i8259s (2); |
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350 | _CPU_ISR_Enable(level); |
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351 | return 1; |
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352 | } |
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353 | |
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354 | int pc386_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
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355 | { |
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356 | *config = internal_config; |
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357 | return 0; |
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358 | } |
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359 | |
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360 | void _ThreadProcessSignalsFromIrq (CPU_Exception_frame* ctx) |
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361 | { |
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362 | /* |
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363 | * If I understand the _Thread_Dispatch routine correctly |
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364 | * I do not see how this routine can be called given the |
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365 | * actual code. I plan to use this so far unused feature |
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366 | * to implement remote debugger ptrace("attach", ...) |
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367 | * command. |
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368 | */ |
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369 | printk(" _ThreadProcessSignalsFromIrq called! mail valette@crf.canon.fr\n"); |
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370 | } |
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