[67a2288] | 1 | /* irq.c |
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| 2 | * |
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| 3 | * This file contains the implementation of the function described in irq.h |
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| 4 | * |
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[fc5490f] | 5 | * Copyright (c) 2009 embedded brains GmbH |
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[a62222fb] | 6 | * Copyright (C) 1998 valette@crf.canon.fr |
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[67a2288] | 7 | * |
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| 8 | * The license and distribution terms for this file may be |
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[8c41855] | 9 | * found in the file LICENSE in this distribution or at |
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[a3c7123] | 10 | * http://www.rtems.com/license/LICENSE. |
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[67a2288] | 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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| 14 | |
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[f9abe50] | 15 | /* so we can see _API_extensions_Run_postswitch */ |
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| 16 | #define __RTEMS_VIOLATE_KERNEL_VISIBILITY__ 1 |
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| 17 | |
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[67a2288] | 18 | #include <bsp.h> |
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[529cebf0] | 19 | #include <bsp/irq.h> |
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[fc5490f] | 20 | #include <bsp/irq-generic.h> |
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| 21 | |
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[f9abe50] | 22 | #include <stdlib.h> |
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[eb562f2] | 23 | #include <rtems/score/apiext.h> |
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[385212f] | 24 | #include <stdio.h> |
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| 25 | #include <inttypes.h> |
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[eb562f2] | 26 | |
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[67a2288] | 27 | /* |
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| 28 | * pointer to the mask representing the additionnal irq vectors |
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| 29 | * that must be disabled when a particular entry is activated. |
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| 30 | * They will be dynamically computed from teh prioruty table given |
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[0ebbf66] | 31 | * in BSP_rtems_irq_mngt_set(); |
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[67a2288] | 32 | * CAUTION : this table is accessed directly by interrupt routine |
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| 33 | * prologue. |
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| 34 | */ |
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[0ebbf66] | 35 | rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_LINES_NUMBER]; |
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[67a2288] | 36 | |
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[385212f] | 37 | uint32_t irq_count[BSP_IRQ_LINES_NUMBER] = {0}; |
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| 38 | |
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| 39 | uint32_t |
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| 40 | BSP_irq_count_dump(FILE *f) |
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| 41 | { |
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| 42 | uint32_t tot = 0; |
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| 43 | int i; |
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| 44 | if ( !f ) |
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| 45 | f = stdout; |
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| 46 | for ( i=0; i<BSP_IRQ_LINES_NUMBER; i++ ) { |
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| 47 | tot += irq_count[i]; |
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| 48 | fprintf(f,"IRQ %2u: %9"PRIu32"\n", i, irq_count[i]); |
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| 49 | } |
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| 50 | return tot; |
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| 51 | } |
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| 52 | |
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[67a2288] | 53 | /*-------------------------------------------------------------------------+ |
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| 54 | | Cache for 1st and 2nd PIC IRQ line's status (enabled or disabled) register. |
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| 55 | +--------------------------------------------------------------------------*/ |
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| 56 | /* |
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| 57 | * lower byte is interrupt mask on the master PIC. |
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| 58 | * while upper bits are interrupt on the slave PIC. |
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| 59 | * This cache is initialized in ldseg.s |
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| 60 | */ |
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[a1c70a2] | 61 | rtems_i8259_masks i8259s_cache = 0xFFFB; |
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[67a2288] | 62 | |
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| 63 | /*-------------------------------------------------------------------------+ |
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[0ebbf66] | 64 | | Function: BSP_irq_disable_at_i8259s |
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[67a2288] | 65 | | Description: Mask IRQ line in appropriate PIC chip. |
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| 66 | | Global Variables: i8259s_cache |
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| 67 | | Arguments: vector_offset - number of IRQ line to mask. |
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[6128a4a] | 68 | | Returns: Nothing. |
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[67a2288] | 69 | +--------------------------------------------------------------------------*/ |
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[838c82b] | 70 | int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine) |
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[67a2288] | 71 | { |
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[c83c325] | 72 | unsigned short mask; |
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| 73 | rtems_interrupt_level level; |
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[67a2288] | 74 | |
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[0ebbf66] | 75 | if ( ((int)irqLine < BSP_LOWEST_OFFSET) || |
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[ad2cefe] | 76 | ((int)irqLine > BSP_MAX_ON_i8259S ) |
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[67a2288] | 77 | ) |
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| 78 | return 1; |
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[6128a4a] | 79 | |
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[c83c325] | 80 | rtems_interrupt_disable(level); |
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[6128a4a] | 81 | |
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[67a2288] | 82 | mask = 1 << irqLine; |
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| 83 | i8259s_cache |= mask; |
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[6128a4a] | 84 | |
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[67a2288] | 85 | if (irqLine < 8) |
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| 86 | { |
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| 87 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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| 88 | } |
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| 89 | else |
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| 90 | { |
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[783e8322] | 91 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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[67a2288] | 92 | } |
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[c83c325] | 93 | rtems_interrupt_enable(level); |
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[67a2288] | 94 | |
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| 95 | return 0; |
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[6128a4a] | 96 | } |
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[67a2288] | 97 | |
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| 98 | /*-------------------------------------------------------------------------+ |
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[0ebbf66] | 99 | | Function: BSP_irq_enable_at_i8259s |
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[67a2288] | 100 | | Description: Unmask IRQ line in appropriate PIC chip. |
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| 101 | | Global Variables: i8259s_cache |
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| 102 | | Arguments: irqLine - number of IRQ line to mask. |
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[6128a4a] | 103 | | Returns: Nothing. |
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[67a2288] | 104 | +--------------------------------------------------------------------------*/ |
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[838c82b] | 105 | int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine) |
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[67a2288] | 106 | { |
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[c83c325] | 107 | unsigned short mask; |
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| 108 | rtems_interrupt_level level; |
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[67a2288] | 109 | |
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[0ebbf66] | 110 | if ( ((int)irqLine < BSP_LOWEST_OFFSET) || |
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[ad2cefe] | 111 | ((int)irqLine > BSP_MAX_ON_i8259S ) |
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[67a2288] | 112 | ) |
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| 113 | return 1; |
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| 114 | |
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[c83c325] | 115 | rtems_interrupt_disable(level); |
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[6128a4a] | 116 | |
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[67a2288] | 117 | mask = ~(1 << irqLine); |
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| 118 | i8259s_cache &= mask; |
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[6128a4a] | 119 | |
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[67a2288] | 120 | if (irqLine < 8) |
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| 121 | { |
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| 122 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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| 123 | } |
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| 124 | else |
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| 125 | { |
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[783e8322] | 126 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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[67a2288] | 127 | } |
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[c83c325] | 128 | rtems_interrupt_enable(level); |
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[67a2288] | 129 | |
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| 130 | return 0; |
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| 131 | } /* mask_irq */ |
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| 132 | |
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[838c82b] | 133 | int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine) |
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[67a2288] | 134 | { |
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| 135 | unsigned short mask; |
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| 136 | |
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[0ebbf66] | 137 | if ( ((int)irqLine < BSP_LOWEST_OFFSET) || |
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[ad2cefe] | 138 | ((int)irqLine > BSP_MAX_ON_i8259S ) |
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[67a2288] | 139 | ) |
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| 140 | return 1; |
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| 141 | |
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| 142 | mask = (1 << irqLine); |
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| 143 | return (~(i8259s_cache & mask)); |
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| 144 | } |
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[6128a4a] | 145 | |
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[67a2288] | 146 | /*-------------------------------------------------------------------------+ |
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[0ebbf66] | 147 | | Function: BSP_irq_ack_at_i8259s |
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[67a2288] | 148 | | Description: Signal generic End Of Interrupt (EOI) to appropriate PIC. |
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| 149 | | Global Variables: None. |
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| 150 | | Arguments: irqLine - number of IRQ line to acknowledge. |
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[6128a4a] | 151 | | Returns: Nothing. |
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[67a2288] | 152 | +--------------------------------------------------------------------------*/ |
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[838c82b] | 153 | int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine) |
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[67a2288] | 154 | { |
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[0ebbf66] | 155 | if ( ((int)irqLine < BSP_LOWEST_OFFSET) || |
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[ad2cefe] | 156 | ((int)irqLine > BSP_MAX_ON_i8259S ) |
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[67a2288] | 157 | ) |
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| 158 | return 1; |
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| 159 | |
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| 160 | if (irqLine >= 8) { |
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| 161 | outport_byte(PIC_SLAVE_COMMAND_IO_PORT, PIC_EOI); |
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| 162 | } |
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| 163 | outport_byte(PIC_MASTER_COMMAND_IO_PORT, PIC_EOI); |
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| 164 | |
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| 165 | return 0; |
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| 166 | |
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| 167 | } /* ackIRQ */ |
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| 168 | |
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| 169 | /* |
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| 170 | * ------------------------ RTEMS Irq helper functions ---------------- |
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| 171 | */ |
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[6128a4a] | 172 | |
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[fc5490f] | 173 | static rtems_irq_prio irqPrioTable[BSP_IRQ_LINES_NUMBER]={ |
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| 174 | /* |
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| 175 | * actual rpiorities for interrupt : |
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| 176 | * 0 means that only current interrupt is masked |
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| 177 | * 255 means all other interrupts are masked |
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| 178 | * The second entry has a priority of 255 because |
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| 179 | * it is the slave pic entry and is should always remain |
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| 180 | * unmasked. |
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| 181 | */ |
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| 182 | 0,0, |
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| 183 | 255, |
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| 184 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
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| 185 | }; |
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| 186 | |
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[f9abe50] | 187 | static void compute_i8259_masks_from_prio (void) |
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[67a2288] | 188 | { |
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[fc5490f] | 189 | rtems_interrupt_level level; |
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[67a2288] | 190 | unsigned int i; |
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| 191 | unsigned int j; |
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[fc5490f] | 192 | |
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[ad2cefe] | 193 | rtems_interrupt_disable(level); |
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[fc5490f] | 194 | |
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[67a2288] | 195 | /* |
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| 196 | * Always mask at least current interrupt to prevent re-entrance |
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| 197 | */ |
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[fc5490f] | 198 | for (i=0; i < BSP_IRQ_LINES_NUMBER; i++) { |
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[67a2288] | 199 | * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i); |
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[fc5490f] | 200 | for (j = 0; j < BSP_IRQ_LINES_NUMBER; j++) { |
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[67a2288] | 201 | /* |
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| 202 | * Mask interrupts at i8259 level that have a lower priority |
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| 203 | */ |
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[fc5490f] | 204 | if (irqPrioTable [i] > irqPrioTable [j]) { |
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[67a2288] | 205 | * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j); |
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| 206 | } |
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| 207 | } |
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| 208 | } |
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[a62222fb] | 209 | |
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| 210 | rtems_interrupt_enable(level); |
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| 211 | } |
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| 212 | |
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[fc5490f] | 213 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
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[67a2288] | 214 | { |
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[fc5490f] | 215 | BSP_irq_enable_at_i8259s(vector); |
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[6128a4a] | 216 | |
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[fc5490f] | 217 | return RTEMS_SUCCESSFUL; |
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[67a2288] | 218 | } |
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| 219 | |
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[fc5490f] | 220 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
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[67a2288] | 221 | { |
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[fc5490f] | 222 | BSP_irq_disable_at_i8259s(vector); |
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[fe235a1e] | 223 | |
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[fc5490f] | 224 | return RTEMS_SUCCESSFUL; |
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[67a2288] | 225 | } |
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| 226 | |
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[fc5490f] | 227 | rtems_status_code bsp_interrupt_facility_initialize(void) |
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[67a2288] | 228 | { |
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[a62222fb] | 229 | /* |
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[fc5490f] | 230 | * set up internal tables used by rtems interrupt prologue |
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[a62222fb] | 231 | */ |
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[fc5490f] | 232 | compute_i8259_masks_from_prio(); |
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[67a2288] | 233 | |
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[a62222fb] | 234 | /* |
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[fc5490f] | 235 | * must enable slave pic anyway |
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[a62222fb] | 236 | */ |
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[fc5490f] | 237 | BSP_irq_enable_at_i8259s(2); |
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[67a2288] | 238 | |
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[fc5490f] | 239 | return RTEMS_SUCCESSFUL; |
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[67a2288] | 240 | } |
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| 241 | |
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[fc5490f] | 242 | void bsp_interrupt_handler_default(rtems_vector_number vector) |
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[67a2288] | 243 | { |
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[fc5490f] | 244 | printk("spurious interrupt: %u\n", vector); |
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[67a2288] | 245 | } |
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| 246 | |
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[fc5490f] | 247 | void C_dispatch_isr(int vector) |
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[67a2288] | 248 | { |
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[385212f] | 249 | irq_count[vector]++; |
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[fc5490f] | 250 | bsp_interrupt_handler_dispatch(vector); |
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[6128a4a] | 251 | } |
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