[1ecb21d8] | 1 | /* |
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[67a2288] | 2 | * This file contains the implementation of the function described in irq.h |
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[1ecb21d8] | 3 | */ |
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| 4 | |
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| 5 | /* |
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[fc5490f] | 6 | * Copyright (c) 2009 embedded brains GmbH |
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[a62222fb] | 7 | * Copyright (C) 1998 valette@crf.canon.fr |
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[67a2288] | 8 | * |
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| 9 | * The license and distribution terms for this file may be |
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[8c41855] | 10 | * found in the file LICENSE in this distribution or at |
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[c499856] | 11 | * http://www.rtems.org/license/LICENSE. |
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[67a2288] | 12 | */ |
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| 13 | |
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| 14 | #include <bsp.h> |
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[529cebf0] | 15 | #include <bsp/irq.h> |
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[fc5490f] | 16 | #include <bsp/irq-generic.h> |
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| 17 | |
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[f9abe50] | 18 | #include <stdlib.h> |
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[385212f] | 19 | #include <stdio.h> |
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| 20 | #include <inttypes.h> |
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[eb562f2] | 21 | |
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[67a2288] | 22 | /* |
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| 23 | * pointer to the mask representing the additionnal irq vectors |
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| 24 | * that must be disabled when a particular entry is activated. |
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| 25 | * They will be dynamically computed from teh prioruty table given |
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[0ebbf66] | 26 | * in BSP_rtems_irq_mngt_set(); |
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[67a2288] | 27 | * CAUTION : this table is accessed directly by interrupt routine |
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| 28 | * prologue. |
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| 29 | */ |
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[0ebbf66] | 30 | rtems_i8259_masks irq_mask_or_tbl[BSP_IRQ_LINES_NUMBER]; |
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[67a2288] | 31 | |
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[385212f] | 32 | uint32_t irq_count[BSP_IRQ_LINES_NUMBER] = {0}; |
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| 33 | |
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| 34 | uint32_t |
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| 35 | BSP_irq_count_dump(FILE *f) |
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| 36 | { |
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| 37 | uint32_t tot = 0; |
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| 38 | int i; |
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| 39 | if ( !f ) |
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| 40 | f = stdout; |
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| 41 | for ( i=0; i<BSP_IRQ_LINES_NUMBER; i++ ) { |
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| 42 | tot += irq_count[i]; |
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| 43 | fprintf(f,"IRQ %2u: %9"PRIu32"\n", i, irq_count[i]); |
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| 44 | } |
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| 45 | return tot; |
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| 46 | } |
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| 47 | |
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[67a2288] | 48 | /*-------------------------------------------------------------------------+ |
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| 49 | | Cache for 1st and 2nd PIC IRQ line's status (enabled or disabled) register. |
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| 50 | +--------------------------------------------------------------------------*/ |
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| 51 | /* |
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| 52 | * lower byte is interrupt mask on the master PIC. |
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| 53 | * while upper bits are interrupt on the slave PIC. |
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| 54 | * This cache is initialized in ldseg.s |
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| 55 | */ |
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[a1c70a2] | 56 | rtems_i8259_masks i8259s_cache = 0xFFFB; |
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[f91fbbf4] | 57 | rtems_i8259_masks i8259s_super_imr = 0xFFFB; |
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[67a2288] | 58 | |
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| 59 | /*-------------------------------------------------------------------------+ |
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[0ebbf66] | 60 | | Function: BSP_irq_disable_at_i8259s |
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[67a2288] | 61 | | Description: Mask IRQ line in appropriate PIC chip. |
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| 62 | | Global Variables: i8259s_cache |
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| 63 | | Arguments: vector_offset - number of IRQ line to mask. |
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[6128a4a] | 64 | | Returns: Nothing. |
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[67a2288] | 65 | +--------------------------------------------------------------------------*/ |
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[838c82b] | 66 | int BSP_irq_disable_at_i8259s (const rtems_irq_number irqLine) |
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[67a2288] | 67 | { |
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[c83c325] | 68 | unsigned short mask; |
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| 69 | rtems_interrupt_level level; |
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[67a2288] | 70 | |
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[0ebbf66] | 71 | if ( ((int)irqLine < BSP_LOWEST_OFFSET) || |
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[ad2cefe] | 72 | ((int)irqLine > BSP_MAX_ON_i8259S ) |
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[67a2288] | 73 | ) |
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| 74 | return 1; |
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[6128a4a] | 75 | |
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[c83c325] | 76 | rtems_interrupt_disable(level); |
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[6128a4a] | 77 | |
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[67a2288] | 78 | mask = 1 << irqLine; |
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| 79 | i8259s_cache |= mask; |
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[f91fbbf4] | 80 | i8259s_super_imr |= mask; |
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[6128a4a] | 81 | |
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[67a2288] | 82 | if (irqLine < 8) |
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| 83 | { |
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| 84 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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| 85 | } |
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| 86 | else |
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| 87 | { |
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[783e8322] | 88 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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[67a2288] | 89 | } |
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[c83c325] | 90 | rtems_interrupt_enable(level); |
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[67a2288] | 91 | |
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| 92 | return 0; |
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[6128a4a] | 93 | } |
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[67a2288] | 94 | |
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| 95 | /*-------------------------------------------------------------------------+ |
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[0ebbf66] | 96 | | Function: BSP_irq_enable_at_i8259s |
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[67a2288] | 97 | | Description: Unmask IRQ line in appropriate PIC chip. |
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| 98 | | Global Variables: i8259s_cache |
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| 99 | | Arguments: irqLine - number of IRQ line to mask. |
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[6128a4a] | 100 | | Returns: Nothing. |
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[67a2288] | 101 | +--------------------------------------------------------------------------*/ |
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[838c82b] | 102 | int BSP_irq_enable_at_i8259s (const rtems_irq_number irqLine) |
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[67a2288] | 103 | { |
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[c83c325] | 104 | unsigned short mask; |
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| 105 | rtems_interrupt_level level; |
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[67a2288] | 106 | |
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[0ebbf66] | 107 | if ( ((int)irqLine < BSP_LOWEST_OFFSET) || |
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[ad2cefe] | 108 | ((int)irqLine > BSP_MAX_ON_i8259S ) |
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[67a2288] | 109 | ) |
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| 110 | return 1; |
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| 111 | |
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[c83c325] | 112 | rtems_interrupt_disable(level); |
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[6128a4a] | 113 | |
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[67a2288] | 114 | mask = ~(1 << irqLine); |
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| 115 | i8259s_cache &= mask; |
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[f91fbbf4] | 116 | i8259s_super_imr &= mask; |
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[6128a4a] | 117 | |
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[67a2288] | 118 | if (irqLine < 8) |
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| 119 | { |
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| 120 | outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); |
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| 121 | } |
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| 122 | else |
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| 123 | { |
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[783e8322] | 124 | outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); |
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[67a2288] | 125 | } |
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[c83c325] | 126 | rtems_interrupt_enable(level); |
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[67a2288] | 127 | |
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| 128 | return 0; |
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| 129 | } /* mask_irq */ |
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| 130 | |
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[838c82b] | 131 | int BSP_irq_enabled_at_i8259s (const rtems_irq_number irqLine) |
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[67a2288] | 132 | { |
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| 133 | unsigned short mask; |
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| 134 | |
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[0ebbf66] | 135 | if ( ((int)irqLine < BSP_LOWEST_OFFSET) || |
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[ad2cefe] | 136 | ((int)irqLine > BSP_MAX_ON_i8259S ) |
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[67a2288] | 137 | ) |
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| 138 | return 1; |
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| 139 | |
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| 140 | mask = (1 << irqLine); |
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| 141 | return (~(i8259s_cache & mask)); |
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| 142 | } |
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[6128a4a] | 143 | |
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[67a2288] | 144 | /*-------------------------------------------------------------------------+ |
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[0ebbf66] | 145 | | Function: BSP_irq_ack_at_i8259s |
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[67a2288] | 146 | | Description: Signal generic End Of Interrupt (EOI) to appropriate PIC. |
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| 147 | | Global Variables: None. |
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| 148 | | Arguments: irqLine - number of IRQ line to acknowledge. |
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[6128a4a] | 149 | | Returns: Nothing. |
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[67a2288] | 150 | +--------------------------------------------------------------------------*/ |
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[838c82b] | 151 | int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine) |
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[67a2288] | 152 | { |
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[0ebbf66] | 153 | if ( ((int)irqLine < BSP_LOWEST_OFFSET) || |
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[ad2cefe] | 154 | ((int)irqLine > BSP_MAX_ON_i8259S ) |
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[67a2288] | 155 | ) |
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| 156 | return 1; |
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| 157 | |
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| 158 | if (irqLine >= 8) { |
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| 159 | outport_byte(PIC_SLAVE_COMMAND_IO_PORT, PIC_EOI); |
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| 160 | } |
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| 161 | outport_byte(PIC_MASTER_COMMAND_IO_PORT, PIC_EOI); |
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| 162 | |
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| 163 | return 0; |
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| 164 | |
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| 165 | } /* ackIRQ */ |
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| 166 | |
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| 167 | /* |
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| 168 | * ------------------------ RTEMS Irq helper functions ---------------- |
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| 169 | */ |
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[6128a4a] | 170 | |
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[fc5490f] | 171 | static rtems_irq_prio irqPrioTable[BSP_IRQ_LINES_NUMBER]={ |
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| 172 | /* |
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[41572c4] | 173 | * actual priorities for each interrupt source: |
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[fc5490f] | 174 | * 0 means that only current interrupt is masked |
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| 175 | * 255 means all other interrupts are masked |
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| 176 | * The second entry has a priority of 255 because |
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| 177 | * it is the slave pic entry and is should always remain |
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| 178 | * unmasked. |
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| 179 | */ |
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| 180 | 0,0, |
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| 181 | 255, |
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| 182 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 |
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| 183 | }; |
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| 184 | |
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[f9abe50] | 185 | static void compute_i8259_masks_from_prio (void) |
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[67a2288] | 186 | { |
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[fc5490f] | 187 | rtems_interrupt_level level; |
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[67a2288] | 188 | unsigned int i; |
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| 189 | unsigned int j; |
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[fc5490f] | 190 | |
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[ad2cefe] | 191 | rtems_interrupt_disable(level); |
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[fc5490f] | 192 | |
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[67a2288] | 193 | /* |
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| 194 | * Always mask at least current interrupt to prevent re-entrance |
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| 195 | */ |
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[fc5490f] | 196 | for (i=0; i < BSP_IRQ_LINES_NUMBER; i++) { |
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[67a2288] | 197 | * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i); |
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[fc5490f] | 198 | for (j = 0; j < BSP_IRQ_LINES_NUMBER; j++) { |
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[67a2288] | 199 | /* |
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| 200 | * Mask interrupts at i8259 level that have a lower priority |
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| 201 | */ |
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[fc5490f] | 202 | if (irqPrioTable [i] > irqPrioTable [j]) { |
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[67a2288] | 203 | * ((unsigned short*) &irq_mask_or_tbl[i]) |= (1 << j); |
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| 204 | } |
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| 205 | } |
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| 206 | } |
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[a62222fb] | 207 | |
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| 208 | rtems_interrupt_enable(level); |
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| 209 | } |
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| 210 | |
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[fc5490f] | 211 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
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[67a2288] | 212 | { |
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[fc5490f] | 213 | BSP_irq_enable_at_i8259s(vector); |
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[6128a4a] | 214 | |
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[fc5490f] | 215 | return RTEMS_SUCCESSFUL; |
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[67a2288] | 216 | } |
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| 217 | |
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[fc5490f] | 218 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
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[67a2288] | 219 | { |
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[fc5490f] | 220 | BSP_irq_disable_at_i8259s(vector); |
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[fe235a1e] | 221 | |
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[fc5490f] | 222 | return RTEMS_SUCCESSFUL; |
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[67a2288] | 223 | } |
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| 224 | |
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[fc5490f] | 225 | rtems_status_code bsp_interrupt_facility_initialize(void) |
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[67a2288] | 226 | { |
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[a62222fb] | 227 | /* |
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[fc5490f] | 228 | * set up internal tables used by rtems interrupt prologue |
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[a62222fb] | 229 | */ |
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[fc5490f] | 230 | compute_i8259_masks_from_prio(); |
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[67a2288] | 231 | |
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[a62222fb] | 232 | /* |
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[fc5490f] | 233 | * must enable slave pic anyway |
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[a62222fb] | 234 | */ |
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[fc5490f] | 235 | BSP_irq_enable_at_i8259s(2); |
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[67a2288] | 236 | |
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[fc5490f] | 237 | return RTEMS_SUCCESSFUL; |
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[67a2288] | 238 | } |
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| 239 | |
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[fc5490f] | 240 | void C_dispatch_isr(int vector) |
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[67a2288] | 241 | { |
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[385212f] | 242 | irq_count[vector]++; |
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[fc5490f] | 243 | bsp_interrupt_handler_dispatch(vector); |
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[6128a4a] | 244 | } |
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